eth_err_inject Entity Reference

Entities
rtl	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
numeric_std

Ports
clk	in std_logic
rst	in std_logic
rate_r	in std_logic_vector ( 15 downto 0 )
force_r	in std_logic
reset_r	in std_logic
count_r	out std_logic_vector ( 23 downto 0 )
rate_t	in std_logic_vector ( 15 downto 0 )
force_t	in std_logic
reset_t	in std_logic
count_t	out std_logic_vector ( 23 downto 0 )
mac_tx_data	out std_logic_vector ( 7 downto 0 )
mac_tx_valid	out std_logic
mac_tx_last	out std_logic
mac_tx_error	out std_logic
mac_tx_ready	in std_logic
mac_rx_data	in std_logic_vector ( 7 downto 0 )
mac_rx_valid	in std_logic
mac_rx_last	in std_logic
mac_rx_error	in std_logic
ipb_tx_data	in std_logic_vector ( 7 downto 0 )
ipb_tx_valid	in std_logic
ipb_tx_last	in std_logic
ipb_tx_error	in std_logic
ipb_tx_ready	out std_logic
ipb_rx_data	out std_logic_vector ( 7 downto 0 )
ipb_rx_valid	out std_logic
ipb_rx_last	out std_logic
ipb_rx_error	out std_logic

Member Data Documentation

clk

clk in std_logic

Port

count_r

count_r out std_logic_vector ( 23 downto 0 )

Port

count_t

count_t out std_logic_vector ( 23 downto 0 )

Port

force_r

force_r in std_logic

Port

force_t

force_t in std_logic

Port

IEEE

IEEE

Library

ipb_rx_data

ipb_rx_data out std_logic_vector ( 7 downto 0 )

Port

ipb_rx_error

ipb_rx_error out std_logic

Port

ipb_rx_last

ipb_rx_last out std_logic

Port

ipb_rx_valid

ipb_rx_valid out std_logic

Port

ipb_tx_data

ipb_tx_data in std_logic_vector ( 7 downto 0 )

Port

ipb_tx_error

ipb_tx_error in std_logic

Port

ipb_tx_last

ipb_tx_last in std_logic

Port

ipb_tx_ready

ipb_tx_ready out std_logic

Port

ipb_tx_valid

ipb_tx_valid in std_logic

Port

mac_rx_data

mac_rx_data in std_logic_vector ( 7 downto 0 )

Port

mac_rx_error

mac_rx_error in std_logic

Port

mac_rx_last

mac_rx_last in std_logic

Port

mac_rx_valid

mac_rx_valid in std_logic

Port

mac_tx_data

mac_tx_data out std_logic_vector ( 7 downto 0 )

Port

mac_tx_error

mac_tx_error out std_logic

Port

mac_tx_last

mac_tx_last out std_logic

Port

mac_tx_ready

mac_tx_ready in std_logic

Port

mac_tx_valid

mac_tx_valid out std_logic

Port

numeric_std

numeric_std

Package

rate_r

rate_r in std_logic_vector ( 15 downto 0 )

Port

rate_t

rate_t in std_logic_vector ( 15 downto 0 )

Port

reset_r

reset_r in std_logic

Port

reset_t

reset_t in std_logic

Port

rst

rst in std_logic

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/hdl/eth_err_inject.vhd