eth_mac_shim Entity Reference

Entities
rtl	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
VComponents
emac_hostbus_decl	Package <emac_hostbus_decl>

Ports
clk125	in std_logic
rst	in std_logic
axi_tx_data	in std_logic_vector ( 7 downto 0 )
axi_tx_valid	in std_logic
axi_tx_last	in std_logic
axi_tx_error	in std_logic
axi_tx_ready	out std_logic
axi_rx_data	out std_logic_vector ( 7 downto 0 )
axi_rx_valid	out std_logic
axi_rx_last	out std_logic
axi_rx_error	out std_logic
v5_txd	out std_logic_vector ( 7 downto 0 )
v5_txdvld	out std_logic
v5_txack	in std_logic
v5_rxd	in std_logic_vector ( 7 downto 0 )
v5_rxdvld	in std_logic
v5_rxgoodframe	in std_logic
v5_rxbadframe	in std_logic

Member Data Documentation

axi_rx_data

axi_rx_data out std_logic_vector ( 7 downto 0 )

Port

axi_rx_error

axi_rx_error out std_logic

Port

axi_rx_last

axi_rx_last out std_logic

Port

axi_rx_valid

axi_rx_valid out std_logic

Port

axi_tx_data

axi_tx_data in std_logic_vector ( 7 downto 0 )

Port

axi_tx_error

axi_tx_error in std_logic

Port

axi_tx_last

axi_tx_last in std_logic

Port

axi_tx_ready

axi_tx_ready out std_logic

Port

axi_tx_valid

axi_tx_valid in std_logic

Port

clk125

clk125 in std_logic

Port

emac_hostbus_decl

emac_hostbus_decl

Package

ieee

ieee

Library

rst

rst in std_logic

Port

std_logic_1164

std_logic_1164

Package

unisim

unisim

Library

v5_rxbadframe

v5_rxbadframe in std_logic

Port

v5_rxd

v5_rxd in std_logic_vector ( 7 downto 0 )

Port

v5_rxdvld

v5_rxdvld in std_logic

Port

v5_rxgoodframe

v5_rxgoodframe in std_logic

Port

v5_txack

v5_txack in std_logic

Port

v5_txd

v5_txd out std_logic_vector ( 7 downto 0 )

Port

v5_txdvld

v5_txdvld out std_logic

Port

VComponents

VComponents

Package

---

The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/hdl/eth_mac_shim.vhd