My Project  v0.0.16
Generics | Ports | Libraries | Use Clauses
eth_mac_sim Entity Reference
Inheritance diagram for eth_mac_sim:
Inheritance graph
[legend]

Entities

behavioural  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 

Generics

MULTI_PACKET  boolean := false

Ports

clk   in std_logic
rst   in std_logic
tx_data   in std_logic_vector ( 7 downto 0 )
tx_valid   in std_logic
tx_last   in std_logic
tx_error   in std_logic
tx_ready   out std_logic
rx_data   out std_logic_vector ( 7 downto 0 )
rx_valid   out std_logic
rx_last   out std_logic
rx_error   out std_logic

Member Data Documentation

◆ clk

clk in std_logic
Port

◆ ieee

ieee
Library

◆ MULTI_PACKET

MULTI_PACKET boolean := false
Generic

◆ numeric_std

numeric_std
Package

◆ rst

rst in std_logic
Port

◆ rx_data

rx_data out std_logic_vector ( 7 downto 0 )
Port

◆ rx_error

rx_error out std_logic
Port

◆ rx_last

rx_last out std_logic
Port

◆ rx_valid

rx_valid out std_logic
Port

◆ std_logic_1164

std_logic_1164
Package

◆ tx_data

tx_data in std_logic_vector ( 7 downto 0 )
Port

◆ tx_error

tx_error in std_logic
Port

◆ tx_last

tx_last in std_logic
Port

◆ tx_ready

tx_ready out std_logic
Port

◆ tx_valid

tx_valid in std_logic
Port

The documentation for this class was generated from the following file: