rtl Architecture Reference

Components
tri_mode_eth_mac_v5_4

Signals
gmii_txd	std_logic_vector ( 7 downto 0 )
gmii_rxd	std_logic_vector ( 7 downto 0 )
gmii_tx_en	std_logic
gmii_tx_er	std_logic
gmii_rx_dv	std_logic
gmii_rx_er	std_logic
gmii_rx_clk	std_logic
clkin	std_logic
clk125	std_logic
gtpclkout	std_logic
gtpclkout_buf	std_logic
rstn	std_logic
status	std_logic_vector ( 15 downto 0 )

Instantiations
ibuf0	ibufds
bufio0	bufio2
bufg0	bufg
mac	tri_mode_eth_mac_v5_4
phy	gig_eth_pcs_pma_v11_4_block
ibuf0	ibufds
bufio0	bufio2
bufg0	bufg
mac	tri_mode_eth_mac_v5_4
phy	gig_eth_pcs_pma_v11_4_block

Member Data Documentation

bufg0 [1/2]

bufg0 bufg

Instantiation

bufg0 [2/2]

bufg0 bufg

Instantiation

bufio0 [1/2]

bufio0 bufio2

Instantiation

bufio0 [2/2]

bufio0 bufio2

Instantiation

clk125

clk125 std_logic

Signal

clkin

clkin std_logic

Signal

gmii_rx_clk

gmii_rx_clk std_logic

Signal

gmii_rx_dv

gmii_rx_dv std_logic

Signal

gmii_rx_er

gmii_rx_er std_logic

Signal

gmii_rxd

gmii_rxd std_logic_vector ( 7 downto 0 )

Signal

gmii_tx_en

gmii_tx_en std_logic

Signal

gmii_tx_er

gmii_tx_er std_logic

Signal

gmii_txd

gmii_txd std_logic_vector ( 7 downto 0 )

Signal

gtpclkout

gtpclkout std_logic

Signal

gtpclkout_buf

gtpclkout_buf std_logic

Signal

ibuf0 [1/2]

ibuf0 ibufds

Instantiation

ibuf0 [2/2]

ibuf0 ibufds

Instantiation

mac [1/2]

mac tri_mode_eth_mac_v5_4

Instantiation

mac [2/2]

mac tri_mode_eth_mac_v5_4

Instantiation

phy [1/2]

phy gig_eth_pcs_pma_v11_4_block

Instantiation

phy [2/2]

phy gig_eth_pcs_pma_v11_4_block

Instantiation

rstn

rstn std_logic

Signal

status

status std_logic_vector ( 15 downto 0 )

Signal

tri_mode_eth_mac_v5_4

tri_mode_eth_mac_v5_4

Component

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/hdl/eth_s6_1000basex.vhd