rtl Architecture Reference

Processes
PROCESS_264	( rx_clk_io )
PROCESS_265	( clk125 )
PROCESS_266	( rx_clk )
PROCESS_824	( rx_clk_io )
PROCESS_825	( clk125 )
PROCESS_826	( rx_clk )

Components
tri_mode_eth_mac_v5_4
mac_fifo_axi4	<Entity mac_fifo_axi4>

Signals
rx_clk	std_logic
rx_clk_io	std_logic
clk125n	std_logic
txd_e	std_logic_vector ( 7 downto 0 )
rxd_r	std_logic_vector ( 7 downto 0 )
tx_en_e	std_logic
tx_er_e	std_logic
rx_dv_r	std_logic
rx_er_r	std_logic
gmii_rxd_del	std_logic_vector ( 7 downto 0 )
gmii_rx_dv_del	std_logic
gmii_rx_er_del	std_logic
rx_data_e	std_logic_vector ( 7 downto 0 )
rx_valid_e	std_logic
rx_last_e	std_logic
rx_user_e	std_logic
rx_rst	std_logic
rstn	std_logic
rx_user_f	std_logic_vector ( 0 downto 0 )
rx_user_ef	std_logic_vector ( 0 downto 0 )
rx_valid_f	std_logic
rx_valid_d	std_logic

Instantiations
bufio0	bufio2
bufg0	bufg
iodelay	iodelay2
iodelay_dv	iodelay2
iodelay_er	iodelay2
oddr0	oddr2
emac0	tri_mode_eth_mac_v5_4
fifo	mac_fifo_axi4 <Entity mac_fifo_axi4>
bufio0	bufio2
bufg0	bufg
iodelay	iodelay2
iodelay_dv	iodelay2
iodelay_er	iodelay2
oddr0	oddr2
emac0	tri_mode_eth_mac_v5_4
fifo	mac_fifo_axi4 <Entity mac_fifo_axi4>

Member Function Documentation

PROCESS_264()

PROCESS_264

(

rx_clk_io

)

PROCESS_265()

PROCESS_265 (   clk125   )

Process

PROCESS_266()

PROCESS_266

(

rx_clk

)

PROCESS_824()

PROCESS_824

(

rx_clk_io

)

PROCESS_825()

PROCESS_825 (   clk125   )

Process

PROCESS_826()

PROCESS_826

(

rx_clk

)

Member Data Documentation

bufg0 [1/2]

bufg0 bufg

Instantiation

bufg0 [2/2]

bufg0 bufg

Instantiation

bufio0 [1/2]

bufio0 bufio2

Instantiation

bufio0 [2/2]

bufio0 bufio2

Instantiation

clk125n

clk125n std_logic

Signal

emac0 [1/2]

emac0 tri_mode_eth_mac_v5_4

Instantiation

emac0 [2/2]

emac0 tri_mode_eth_mac_v5_4

Instantiation

fifo [1/2]

fifo mac_fifo_axi4

Instantiation

fifo [2/2]

fifo mac_fifo_axi4

Instantiation

gmii_rx_dv_del

gmii_rx_dv_del std_logic

Signal

gmii_rx_er_del

gmii_rx_er_del std_logic

Signal

gmii_rxd_del

gmii_rxd_del std_logic_vector ( 7 downto 0 )

Signal

iodelay [1/2]

iodelay iodelay2

Instantiation

iodelay [2/2]

iodelay iodelay2

Instantiation

iodelay_dv [1/2]

iodelay_dv iodelay2

Instantiation

iodelay_dv [2/2]

iodelay_dv iodelay2

Instantiation

iodelay_er [1/2]

iodelay_er iodelay2

Instantiation

iodelay_er [2/2]

iodelay_er iodelay2

Instantiation

mac_fifo_axi4

mac_fifo_axi4

Component

oddr0 [1/2]

oddr0 oddr2

Instantiation

oddr0 [2/2]

oddr0 oddr2

Instantiation

rstn

rstn std_logic

Signal

rx_clk

rx_clk std_logic

Signal

rx_clk_io

rx_clk_io std_logic

Signal

rx_data_e

rx_data_e std_logic_vector ( 7 downto 0 )

Signal

rx_dv_r

rx_dv_r std_logic

Signal

rx_er_r

rx_er_r std_logic

Signal

rx_last_e

rx_last_e std_logic

Signal

rx_rst

rx_rst std_logic

Signal

rx_user_e

rx_user_e std_logic

Signal

rx_user_ef

rx_user_ef std_logic_vector ( 0 downto 0 )

Signal

rx_user_f

rx_user_f std_logic_vector ( 0 downto 0 )

Signal

rx_valid_d

rx_valid_d std_logic

Signal

rx_valid_e

rx_valid_e std_logic

Signal

rx_valid_f

rx_valid_f std_logic

Signal

rxd_r

rxd_r std_logic_vector ( 7 downto 0 )

Signal

tri_mode_eth_mac_v5_4

tri_mode_eth_mac_v5_4

Component

tx_en_e

tx_en_e std_logic

Signal

tx_er_e

tx_er_e std_logic

Signal

txd_e

txd_e std_logic_vector ( 7 downto 0 )

Signal

---

The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/hdl/eth_s6_gmii.vhd