eth_v6_gmii Entity Reference

Libraries
ieee
unisim

Use Clauses
std_logic_1164
VComponents
emac_hostbus_decl	Package <emac_hostbus_decl>

Generics
IODEL	integer := 20

Ports
clk125	in std_logic
clk200	in std_logic
rst	in std_logic
locked	in std_logic
gmii_gtx_clk	out std_logic
gmii_txd	out std_logic_vector ( 7 downto 0 )
gmii_tx_en	out std_logic
gmii_tx_er	out std_logic
gmii_rx_clk	in std_logic
gmii_rxd	in std_logic_vector ( 7 downto 0 )
gmii_rx_dv	in std_logic
gmii_rx_er	in std_logic
txd	in std_logic_vector ( 7 downto 0 )
txdvld	in std_logic
txack	out std_logic
rxclko	out std_logic
rxd	out std_logic_vector ( 7 downto 0 )
rxdvld	out std_logic
rxgoodframe	out std_logic
rxbadframe	out std_logic hostbus_in

Member Data Documentation

clk125

clk125 in std_logic

Port

clk200

clk200 in std_logic

Port

emac_hostbus_decl

emac_hostbus_decl

Package

gmii_gtx_clk

gmii_gtx_clk out std_logic

Port

gmii_rx_clk

gmii_rx_clk in std_logic

Port

gmii_rx_dv

gmii_rx_dv in std_logic

Port

gmii_rx_er

gmii_rx_er in std_logic

Port

gmii_rxd

gmii_rxd in std_logic_vector ( 7 downto 0 )

Port

gmii_tx_en

gmii_tx_en out std_logic

Port

gmii_tx_er

gmii_tx_er out std_logic

Port

gmii_txd

gmii_txd out std_logic_vector ( 7 downto 0 )

Port

ieee

ieee

Library

IODEL

IODEL integer := 20

Generic

locked

locked in std_logic

Port

rst

rst in std_logic

Port

rxbadframe

rxbadframe out std_logic hostbus_in

Port

rxclko

rxclko out std_logic

Port

rxd

rxd out std_logic_vector ( 7 downto 0 )

Port

rxdvld

rxdvld out std_logic

Port

rxgoodframe

rxgoodframe out std_logic

Port

std_logic_1164

std_logic_1164

Package

txack

txack out std_logic

Port

txd

txd in std_logic_vector ( 7 downto 0 )

Port

txdvld

txdvld in std_logic

Port

unisim

unisim

Library

VComponents

VComponents

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/hdl/eth_v6_gmii.vhd