gig_eth_pcs_pma_basex_v15_0_transceiver Entity Reference

Inheritance diagram for gig_eth_pcs_pma_basex_v15_0_transceiver:

Collaboration diagram for gig_eth_pcs_pma_basex_v15_0_transceiver:

Entities
wrapper	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
numeric_std
vcomponents

Generics
EXAMPLE_SIMULATION	integer := 0

Ports
mmcm_reset	out std_logic
data_valid	in std_logic
independent_clock	in std_logic
encommaalign	in std_logic
powerdown	in std_logic
usrclk	in std_logic
usrclk2	in std_logic
rxusrclk	in std_logic
rxusrclk2	in std_logic
txreset	in std_logic
txdata	in std_logic_vector ( 7 downto 0 )
txchardispmode	in std_logic
txchardispval	in std_logic
txcharisk	in std_logic
rxreset	in std_logic
rxchariscomma	out std_logic
rxcharisk	out std_logic
rxclkcorcnt	out std_logic_vector ( 2 downto 0 )
rxdata	out std_logic_vector ( 7 downto 0 )
rxdisperr	out std_logic
rxnotintable	out std_logic
rxrundisp	out std_logic
rxbuferr	out std_logic
txbuferr	out std_logic
plllkdet	out std_logic
txoutclk	out std_logic
rxoutclk	out std_logic
txn	out std_logic
txp	out std_logic
rxn	in std_logic
rxp	in std_logic
gtrefclk	in std_logic
gtrefclk_bufg	in std_logic
pmareset	in std_logic
mmcm_locked	in std_logic
resetdone	out std_logic
gt0_rxbyteisaligned_out	out std_logic
gt0_rxbyterealign_out	out std_logic
gt0_rxcommadet_out	out std_logic
gt0_txpolarity_in	in std_logic
gt0_txdiffctrl_in	in std_logic_vector ( 3 downto 0 )
gt0_txinhibit_in	in std_logic
gt0_txpostcursor_in	in std_logic_vector ( 4 downto 0 )
gt0_txprecursor_in	in std_logic_vector ( 4 downto 0 )
gt0_rxpolarity_in	in std_logic
gt0_rxdfelpmreset_in	in std_logic
gt0_rxdfeagcovrden_in	in std_logic
gt0_rxlpmen_in	in std_logic
gt0_txprbssel_in	in std_logic_vector ( 2 downto 0 )
gt0_txprbsforceerr_in	in std_logic
gt0_rxprbscntreset_in	in std_logic
gt0_rxprbserr_out	out std_logic
gt0_rxprbssel_in	in std_logic_vector ( 2 downto 0 )
gt0_loopback_in	in std_logic_vector ( 2 downto 0 )
gt0_txresetdone_out	out std_logic
gt0_rxresetdone_out	out std_logic
gt0_eyescanreset_in	in std_logic
gt0_eyescandataerror_out	out std_logic
gt0_eyescantrigger_in	in std_logic
gt0_rxcdrhold_in	in std_logic
gt0_rxmonitorout_out	out std_logic_vector ( 6 downto 0 )
gt0_rxmonitorsel_in	in std_logic_vector ( 1 downto 0 )
gt0_drpaddr_in	in std_logic_vector ( 8 downto 0 )
gt0_drpclk_in	in std_logic
gt0_drpdi_in	in std_logic_vector ( 15 downto 0 )
gt0_drpdo_out	out std_logic_vector ( 15 downto 0 )
gt0_drpen_in	in std_logic
gt0_drprdy_out	out std_logic
gt0_drpwe_in	in std_logic
gt0_txpmareset_in	in std_logic
gt0_txpcsreset_in	in std_logic
gt0_rxpmareset_in	in std_logic
gt0_rxpcsreset_in	in std_logic
gt0_rxbufreset_in	in std_logic
gt0_rxbufstatus_out	out std_logic_vector ( 2 downto 0 )
gt0_txbufstatus_out	out std_logic_vector ( 1 downto 0 )
gt0_dmonitorout_out	out std_logic_vector ( 7 downto 0 )
gt0_qplloutclk	in std_logic
gt0_qplloutrefclk	in std_logic

Member Data Documentation

data_valid

data_valid in std_logic

Port

encommaalign

encommaalign in std_logic

Port

EXAMPLE_SIMULATION

EXAMPLE_SIMULATION integer := 0

Generic

gt0_dmonitorout_out

gt0_dmonitorout_out out std_logic_vector ( 7 downto 0 )

Port

gt0_drpaddr_in

gt0_drpaddr_in in std_logic_vector ( 8 downto 0 )

Port

gt0_drpclk_in

gt0_drpclk_in in std_logic

Port

gt0_drpdi_in

gt0_drpdi_in in std_logic_vector ( 15 downto 0 )

Port

gt0_drpdo_out

gt0_drpdo_out out std_logic_vector ( 15 downto 0 )

Port

gt0_drpen_in

gt0_drpen_in in std_logic

Port

gt0_drprdy_out

gt0_drprdy_out out std_logic

Port

gt0_drpwe_in

gt0_drpwe_in in std_logic

Port

gt0_eyescandataerror_out

gt0_eyescandataerror_out out std_logic

Port

gt0_eyescanreset_in

gt0_eyescanreset_in in std_logic

Port

gt0_eyescantrigger_in

gt0_eyescantrigger_in in std_logic

Port

gt0_loopback_in

gt0_loopback_in in std_logic_vector ( 2 downto 0 )

Port

gt0_qplloutclk

gt0_qplloutclk in std_logic

Port

gt0_qplloutrefclk

gt0_qplloutrefclk in std_logic

Port

gt0_rxbufreset_in

gt0_rxbufreset_in in std_logic

Port

gt0_rxbufstatus_out

gt0_rxbufstatus_out out std_logic_vector ( 2 downto 0 )

Port

gt0_rxbyteisaligned_out

gt0_rxbyteisaligned_out out std_logic

Port

gt0_rxbyterealign_out

gt0_rxbyterealign_out out std_logic

Port

gt0_rxcdrhold_in

gt0_rxcdrhold_in in std_logic

Port

gt0_rxcommadet_out

gt0_rxcommadet_out out std_logic

Port

gt0_rxdfeagcovrden_in

gt0_rxdfeagcovrden_in in std_logic

Port

gt0_rxdfelpmreset_in

gt0_rxdfelpmreset_in in std_logic

Port

gt0_rxlpmen_in

gt0_rxlpmen_in in std_logic

Port

gt0_rxmonitorout_out

gt0_rxmonitorout_out out std_logic_vector ( 6 downto 0 )

Port

gt0_rxmonitorsel_in

gt0_rxmonitorsel_in in std_logic_vector ( 1 downto 0 )

Port

gt0_rxpcsreset_in

gt0_rxpcsreset_in in std_logic

Port

gt0_rxpmareset_in

gt0_rxpmareset_in in std_logic

Port

gt0_rxpolarity_in

gt0_rxpolarity_in in std_logic

Port

gt0_rxprbscntreset_in

gt0_rxprbscntreset_in in std_logic

Port

gt0_rxprbserr_out

gt0_rxprbserr_out out std_logic

Port

gt0_rxprbssel_in

gt0_rxprbssel_in in std_logic_vector ( 2 downto 0 )

Port

gt0_rxresetdone_out

gt0_rxresetdone_out out std_logic

Port

gt0_txbufstatus_out

gt0_txbufstatus_out out std_logic_vector ( 1 downto 0 )

Port

gt0_txdiffctrl_in

gt0_txdiffctrl_in in std_logic_vector ( 3 downto 0 )

Port

gt0_txinhibit_in

gt0_txinhibit_in in std_logic

Port

gt0_txpcsreset_in

gt0_txpcsreset_in in std_logic

Port

gt0_txpmareset_in

gt0_txpmareset_in in std_logic

Port

gt0_txpolarity_in

gt0_txpolarity_in in std_logic

Port

gt0_txpostcursor_in

gt0_txpostcursor_in in std_logic_vector ( 4 downto 0 )

Port

gt0_txprbsforceerr_in

gt0_txprbsforceerr_in in std_logic

Port

gt0_txprbssel_in

gt0_txprbssel_in in std_logic_vector ( 2 downto 0 )

Port

gt0_txprecursor_in

gt0_txprecursor_in in std_logic_vector ( 4 downto 0 )

Port

gt0_txresetdone_out

gt0_txresetdone_out out std_logic

Port

gtrefclk

gtrefclk in std_logic

Port

gtrefclk_bufg

gtrefclk_bufg in std_logic

Port

ieee

ieee

Library

independent_clock

independent_clock in std_logic

Port

mmcm_locked

mmcm_locked in std_logic

Port

mmcm_reset

mmcm_reset out std_logic

Port

numeric_std

numeric_std

Package

plllkdet

plllkdet out std_logic

Port

pmareset

pmareset in std_logic

Port

powerdown

powerdown in std_logic

Port

resetdone

resetdone out std_logic

Port

rxbuferr

rxbuferr out std_logic

Port

rxchariscomma

rxchariscomma out std_logic

Port

rxcharisk

rxcharisk out std_logic

Port

rxclkcorcnt

rxclkcorcnt out std_logic_vector ( 2 downto 0 )

Port

rxdata

rxdata out std_logic_vector ( 7 downto 0 )

Port

rxdisperr

rxdisperr out std_logic

Port

rxn

rxn in std_logic

Port

rxnotintable

rxnotintable out std_logic

Port

rxoutclk

rxoutclk out std_logic

Port

rxp

rxp in std_logic

Port

rxreset

rxreset in std_logic

Port

rxrundisp

rxrundisp out std_logic

Port

rxusrclk

rxusrclk in std_logic

Port

rxusrclk2

rxusrclk2 in std_logic

Port

std_logic_1164

std_logic_1164

Package

txbuferr

txbuferr out std_logic

Port

txchardispmode

txchardispmode in std_logic

Port

txchardispval

txchardispval in std_logic

Port

txcharisk

txcharisk in std_logic

Port

txdata

txdata in std_logic_vector ( 7 downto 0 )

Port

txn

txn out std_logic

Port

txoutclk

txoutclk out std_logic

Port

txp

txp out std_logic

Port

txreset

txreset in std_logic

Port

unisim

unisim

Library

usrclk

usrclk in std_logic

Port

usrclk2

usrclk2 in std_logic

Port

vcomponents

vcomponents

Package

---

The documentation for this class was generated from the following file:

• ipbus_lib/components/ipbus_eth/firmware/gen_hdl/gig_eth_pcs_pma_basex_v15_0/synth/transceiver/gig_eth_pcs_pma_basex_v15_0_transceiver.vhd