wrapper Architecture Reference

Processes
PROCESS_64	( usrclk2 )
PROCESS_65	( usrclk2 )
PROCESS_66	( usrclk2 )
PROCESS_67	( usrclk )
PROCESS_68	( usrclk )
PROCESS_69	( usrclk2 )
PROCESS_70	( usrclk2 )
PROCESS_71	( usrclk2 )
PROCESS_72	( usrclk2 )
PROCESS_73	( usrclk2 )
PROCESS_74	( usrclk2 )
PROCESS_75	( usrclk2 )
PROCESS_76	( usrclk )
PROCESS_77	( usrclk )
PROCESS_78	( usrclk2 )
PROCESS_79	( usrclk2 )
PROCESS_80	( usrclk2 )
PROCESS_81	( usrclk2 )
PROCESS_625	( usrclk2 )
PROCESS_626	( usrclk2 )
PROCESS_627	( usrclk2 )
PROCESS_628	( usrclk )
PROCESS_629	( usrclk )
PROCESS_630	( usrclk2 )
PROCESS_631	( usrclk2 )
PROCESS_632	( usrclk2 )
PROCESS_633	( usrclk2 )
PROCESS_634	( usrclk2 )
PROCESS_635	( usrclk2 )
PROCESS_636	( usrclk2 )
PROCESS_637	( usrclk )
PROCESS_638	( usrclk )
PROCESS_639	( usrclk2 )
PROCESS_640	( usrclk2 )
PROCESS_641	( usrclk2 )
PROCESS_642	( usrclk2 )

Components
gig_eth_pcs_pma_v11_4_sync_block
gtwizard_v2_3_gbe_init	<Entity gtwizard_v2_3_gbe_init>
gig_eth_pcs_pma_v11_4_reset_sync
gtwizard_v2_4_gth_init

Signals
data_valid_reg	std_logic
data_valid_reg2	std_logic
cplllock	std_logic
gt_reset_rx	std_logic
gt_reset_tx	std_logic
resetdone_tx	std_logic
resetdone_rx	std_logic
pcsreset	std_logic
rxbufstatus	std_logic_vector ( 2 downto 0 )
txbufstatus	std_logic_vector ( 1 downto 0 )
rxbufstatus_reg	std_logic_vector ( 2 downto 0 )
txbufstatus_reg	std_logic_vector ( 1 downto 0 )
rxclkcorcnt_int	std_logic_vector ( 1 downto 0 )
toggle	std_logic
encommaalign_int	std_logic
txreset_int	std_logic
rxreset_int	std_logic
txdata_reg	std_logic_vector ( 7 downto 0 )
txchardispmode_reg	std_logic
txchardispval_reg	std_logic
txcharisk_reg	std_logic
txdata_double	std_logic_vector ( 15 downto 0 )
txchardispmode_double	std_logic_vector ( 1 downto 0 )
txchardispval_double	std_logic_vector ( 1 downto 0 )
txcharisk_double	std_logic_vector ( 1 downto 0 )
txdata_int	std_logic_vector ( 15 downto 0 )
txchardispmode_int	std_logic_vector ( 1 downto 0 )
txchardispval_int	std_logic_vector ( 1 downto 0 )
txcharisk_int	std_logic_vector ( 1 downto 0 )
rxchariscomma_int	std_logic_vector ( 1 downto 0 )
rxcharisk_int	std_logic_vector ( 1 downto 0 )
rxdata_int	std_logic_vector ( 15 downto 0 )
rxdisperr_int	std_logic_vector ( 1 downto 0 )
rxnotintable_int	std_logic_vector ( 1 downto 0 )
rxrundisp_int	std_logic_vector ( 1 downto 0 )
rxchariscomma_reg	std_logic_vector ( 1 downto 0 )
rxcharisk_reg	std_logic_vector ( 1 downto 0 )
rxdata_reg	std_logic_vector ( 15 downto 0 )
rxdisperr_reg	std_logic_vector ( 1 downto 0 )
rxnotintable_reg	std_logic_vector ( 1 downto 0 )
rxrundisp_reg	std_logic_vector ( 1 downto 0 )
rxchariscomma_double	std_logic_vector ( 1 downto 0 )
rxcharisk_double	std_logic_vector ( 1 downto 0 )
rxdata_double	std_logic_vector ( 15 downto 0 )
rxdisperr_double	std_logic_vector ( 1 downto 0 )
rxnotintable_double	std_logic_vector ( 1 downto 0 )
rxrundisp_double	std_logic_vector ( 1 downto 0 )
txpowerdown_int	std_logic_vector ( 1 downto 0 )
rxpowerdown_int	std_logic_vector ( 1 downto 0 )
txpowerdown_reg	std_logic := ' 0 '
txpowerdown_double	std_logic := ' 0 '
txpowerdown	std_logic := ' 0 '
rxpowerdown_reg	std_logic := ' 0 '
rxpowerdown_double	std_logic := ' 0 '
rxpowerdown	std_logic := ' 0 '

Instantiations
reclock_encommaalign	gig_eth_pcs_pma_v11_4_reset_sync
reclock_txreset	gig_eth_pcs_pma_v11_4_reset_sync
reclock_rxreset	gig_eth_pcs_pma_v11_4_reset_sync
gtwizard_inst	gtwizard_v2_3_gbe_init <Entity gtwizard_v2_3_gbe_init>
sync_block_data_valid	gig_eth_pcs_pma_v11_4_sync_block
reclock_encommaalign	gig_eth_pcs_pma_v11_4_reset_sync
reclock_txreset	gig_eth_pcs_pma_v11_4_reset_sync
reclock_rxreset	gig_eth_pcs_pma_v11_4_reset_sync
gtwizard_inst	gtwizard_v2_4_gth_init
sync_block_data_valid	gig_eth_pcs_pma_v11_4_sync_block
reclock_encommaalign	gig_eth_pcs_pma_v11_4_reset_sync
reclock_txreset	gig_eth_pcs_pma_v11_4_reset_sync
reclock_rxreset	gig_eth_pcs_pma_v11_4_reset_sync
gtwizard_inst	gtwizard_v2_3_gbe_init <Entity gtwizard_v2_3_gbe_init>
sync_block_data_valid	gig_eth_pcs_pma_v11_4_sync_block
reclock_encommaalign	gig_eth_pcs_pma_v11_4_reset_sync
reclock_txreset	gig_eth_pcs_pma_v11_4_reset_sync
reclock_rxreset	gig_eth_pcs_pma_v11_4_reset_sync
gtwizard_inst	gtwizard_v2_4_gth_init
sync_block_data_valid	gig_eth_pcs_pma_v11_4_sync_block

Member Function Documentation

PROCESS_625()

PROCESS_625

(

usrclk2

)

PROCESS_626()

PROCESS_626 (   usrclk2   )

Process

PROCESS_627()

PROCESS_627 (   usrclk2   )

Process

PROCESS_628()

PROCESS_628 (   usrclk   )

Process

PROCESS_629()

PROCESS_629 (   usrclk   )

Process

PROCESS_630()

PROCESS_630 (   usrclk2   )

Process

PROCESS_631()

PROCESS_631 (   usrclk2   )

Process

PROCESS_632()

PROCESS_632

(

usrclk2

)

PROCESS_633()

PROCESS_633 (   usrclk2   )

Process

PROCESS_634()

PROCESS_634

(

usrclk2

)

PROCESS_635()

PROCESS_635 (   usrclk2   )

Process

PROCESS_636()

PROCESS_636 (   usrclk2   )

Process

PROCESS_637()

PROCESS_637 (   usrclk   )

Process

PROCESS_638()

PROCESS_638 (   usrclk   )

Process

PROCESS_639()

PROCESS_639 (   usrclk2   )

Process

PROCESS_64()

PROCESS_64

(

usrclk2

)

PROCESS_640()

PROCESS_640 (   usrclk2   )

Process

PROCESS_641()

PROCESS_641

(

usrclk2

)

PROCESS_642()

PROCESS_642 (   usrclk2   )

Process

PROCESS_65()

PROCESS_65 (   usrclk2   )

Process

PROCESS_66()

PROCESS_66 (   usrclk2   )

Process

PROCESS_67()

PROCESS_67 (   usrclk   )

Process

PROCESS_68()

PROCESS_68 (   usrclk   )

Process

PROCESS_69()

PROCESS_69 (   usrclk2   )

Process

PROCESS_70()

PROCESS_70 (   usrclk2   )

Process

PROCESS_71()

PROCESS_71

(

usrclk2

)

PROCESS_72()

PROCESS_72 (   usrclk2   )

Process

PROCESS_73()

PROCESS_73

(

usrclk2

)

PROCESS_74()

PROCESS_74 (   usrclk2   )

Process

PROCESS_75()

PROCESS_75 (   usrclk2   )

Process

PROCESS_76()

PROCESS_76 (   usrclk   )

Process

PROCESS_77()

PROCESS_77 (   usrclk   )

Process

PROCESS_78()

PROCESS_78 (   usrclk2   )

Process

PROCESS_79()

PROCESS_79 (   usrclk2   )

Process

PROCESS_80()

PROCESS_80

(

usrclk2

)

PROCESS_81()

PROCESS_81 (   usrclk2   )

Process

Member Data Documentation

cplllock

cplllock std_logic

Signal

data_valid_reg

data_valid_reg std_logic

Signal

data_valid_reg2

data_valid_reg2 std_logic

Signal

encommaalign_int

encommaalign_int std_logic

Signal

gig_eth_pcs_pma_v11_4_reset_sync

gig_eth_pcs_pma_v11_4_reset_sync

Component

gig_eth_pcs_pma_v11_4_sync_block

gig_eth_pcs_pma_v11_4_sync_block

Component

gt_reset_rx

gt_reset_rx std_logic

Signal

gt_reset_tx

gt_reset_tx std_logic

Signal

gtwizard_inst [1/4]

gtwizard_inst gtwizard_v2_4_gth_init

Instantiation

gtwizard_inst [2/4]

gtwizard_inst gtwizard_v2_4_gth_init

Instantiation

gtwizard_inst [3/4]

gtwizard_inst gtwizard_v2_3_gbe_init

Instantiation

gtwizard_inst [4/4]

gtwizard_inst gtwizard_v2_3_gbe_init

Instantiation

gtwizard_v2_3_gbe_init

gtwizard_v2_3_gbe_init

Component

gtwizard_v2_4_gth_init

gtwizard_v2_4_gth_init

Component

pcsreset

pcsreset std_logic

Signal

reclock_encommaalign [1/4]

reclock_encommaalign gig_eth_pcs_pma_v11_4_reset_sync

Instantiation

reclock_encommaalign [2/4]

reclock_encommaalign gig_eth_pcs_pma_v11_4_reset_sync

Instantiation

reclock_encommaalign [3/4]

reclock_encommaalign gig_eth_pcs_pma_v11_4_reset_sync

Instantiation

reclock_encommaalign [4/4]

reclock_encommaalign gig_eth_pcs_pma_v11_4_reset_sync

Instantiation

reclock_rxreset [1/4]

reclock_rxreset gig_eth_pcs_pma_v11_4_reset_sync

Instantiation

reclock_rxreset [2/4]

reclock_rxreset gig_eth_pcs_pma_v11_4_reset_sync

Instantiation

reclock_rxreset [3/4]

reclock_rxreset gig_eth_pcs_pma_v11_4_reset_sync

Instantiation

reclock_rxreset [4/4]

reclock_rxreset gig_eth_pcs_pma_v11_4_reset_sync

Instantiation

reclock_txreset [1/4]

reclock_txreset gig_eth_pcs_pma_v11_4_reset_sync

Instantiation

reclock_txreset [2/4]

reclock_txreset gig_eth_pcs_pma_v11_4_reset_sync

Instantiation

reclock_txreset [3/4]

reclock_txreset gig_eth_pcs_pma_v11_4_reset_sync

Instantiation

reclock_txreset [4/4]

reclock_txreset gig_eth_pcs_pma_v11_4_reset_sync

Instantiation

resetdone_rx

resetdone_rx std_logic

Signal

resetdone_tx

resetdone_tx std_logic

Signal

rxbufstatus

rxbufstatus std_logic_vector ( 2 downto 0 )

Signal

rxbufstatus_reg

rxbufstatus_reg std_logic_vector ( 2 downto 0 )

Signal

rxchariscomma_double

rxchariscomma_double std_logic_vector ( 1 downto 0 )

Signal

rxchariscomma_int

rxchariscomma_int std_logic_vector ( 1 downto 0 )

Signal

rxchariscomma_reg

rxchariscomma_reg std_logic_vector ( 1 downto 0 )

Signal

rxcharisk_double

rxcharisk_double std_logic_vector ( 1 downto 0 )

Signal

rxcharisk_int

rxcharisk_int std_logic_vector ( 1 downto 0 )

Signal

rxcharisk_reg

rxcharisk_reg std_logic_vector ( 1 downto 0 )

Signal

rxclkcorcnt_int

rxclkcorcnt_int std_logic_vector ( 1 downto 0 )

Signal

rxdata_double

rxdata_double std_logic_vector ( 15 downto 0 )

Signal

rxdata_int

rxdata_int std_logic_vector ( 15 downto 0 )

Signal

rxdata_reg

rxdata_reg std_logic_vector ( 15 downto 0 )

Signal

rxdisperr_double

rxdisperr_double std_logic_vector ( 1 downto 0 )

Signal

rxdisperr_int

rxdisperr_int std_logic_vector ( 1 downto 0 )

Signal

rxdisperr_reg

rxdisperr_reg std_logic_vector ( 1 downto 0 )

Signal

rxnotintable_double

rxnotintable_double std_logic_vector ( 1 downto 0 )

Signal

rxnotintable_int

rxnotintable_int std_logic_vector ( 1 downto 0 )

Signal

rxnotintable_reg

rxnotintable_reg std_logic_vector ( 1 downto 0 )

Signal

rxpowerdown

rxpowerdown std_logic := ' 0 '

Signal

rxpowerdown_double

rxpowerdown_double std_logic := ' 0 '

Signal

rxpowerdown_int

rxpowerdown_int std_logic_vector ( 1 downto 0 )

Signal

rxpowerdown_reg

rxpowerdown_reg std_logic := ' 0 '

Signal

rxreset_int

rxreset_int std_logic

Signal

rxrundisp_double

rxrundisp_double std_logic_vector ( 1 downto 0 )

Signal

rxrundisp_int

rxrundisp_int std_logic_vector ( 1 downto 0 )

Signal

rxrundisp_reg

rxrundisp_reg std_logic_vector ( 1 downto 0 )

Signal

sync_block_data_valid [1/4]

sync_block_data_valid gig_eth_pcs_pma_v11_4_sync_block

Instantiation

sync_block_data_valid [2/4]

sync_block_data_valid gig_eth_pcs_pma_v11_4_sync_block

Instantiation

sync_block_data_valid [3/4]

sync_block_data_valid gig_eth_pcs_pma_v11_4_sync_block

Instantiation

sync_block_data_valid [4/4]

sync_block_data_valid gig_eth_pcs_pma_v11_4_sync_block

Instantiation

toggle

toggle std_logic

Signal

txbufstatus

txbufstatus std_logic_vector ( 1 downto 0 )

Signal

txbufstatus_reg

txbufstatus_reg std_logic_vector ( 1 downto 0 )

Signal

txchardispmode_double

txchardispmode_double std_logic_vector ( 1 downto 0 )

Signal

txchardispmode_int

txchardispmode_int std_logic_vector ( 1 downto 0 )

Signal

txchardispmode_reg

txchardispmode_reg std_logic

Signal

txchardispval_double

txchardispval_double std_logic_vector ( 1 downto 0 )

Signal

txchardispval_int

txchardispval_int std_logic_vector ( 1 downto 0 )

Signal

txchardispval_reg

txchardispval_reg std_logic

Signal

txcharisk_double

txcharisk_double std_logic_vector ( 1 downto 0 )

Signal

txcharisk_int

txcharisk_int std_logic_vector ( 1 downto 0 )

Signal

txcharisk_reg

txcharisk_reg std_logic

Signal

txdata_double

txdata_double std_logic_vector ( 15 downto 0 )

Signal

txdata_int

txdata_int std_logic_vector ( 15 downto 0 )

Signal

txdata_reg

txdata_reg std_logic_vector ( 7 downto 0 )

Signal

txpowerdown

txpowerdown std_logic := ' 0 '

Signal

txpowerdown_double

txpowerdown_double std_logic := ' 0 '

Signal

txpowerdown_int

txpowerdown_int std_logic_vector ( 1 downto 0 )

Signal

txpowerdown_reg

txpowerdown_reg std_logic := ' 0 '

Signal

txreset_int

txreset_int std_logic

Signal

---

The documentation for this class was generated from the following files:

• components/ipbus_eth/firmware/gen_hdl/gig_eth_pcs_pma_v11_4/gig_eth_pcs_pma_v11_4_transceiver.vhd
• components/ipbus_eth/firmware/gen_hdl/gig_eth_pcs_pma_v11_4/gig_eth_pcs_pma_v11_4_transceiver_gth.vhd