gig_eth_pcs_pma_v11_5_block Entity Reference

Inheritance diagram for gig_eth_pcs_pma_v11_5_block:

Collaboration diagram for gig_eth_pcs_pma_v11_5_block:

Entities
block_level	architecture

Libraries
unisim
ieee

Use Clauses
vcomponents
std_logic_1164

Generics
EXAMPLE_SIMULATION	integer := 0

Ports
drpaddr_in	in std_logic_vector ( 8 downto 0 )
drpclk_in	in std_logic
drpdi_in	in std_logic_vector ( 15 downto 0 )
drpdo_out	out std_logic_vector ( 15 downto 0 )
drpen_in	in std_logic
drprdy_out	out std_logic
drpwe_in	in std_logic
gtrefclk	in std_logic
txp	out std_logic
txn	out std_logic
rxp	in std_logic
rxn	in std_logic
txoutclk	out std_logic
resetdone	out std_logic
mmcm_locked	in std_logic
userclk	in std_logic
userclk2	in std_logic
independent_clock_bufg	in std_logic
pma_reset	in std_logic
gmii_txd	in std_logic_vector ( 7 downto 0 )
gmii_tx_en	in std_logic
gmii_tx_er	in std_logic
gmii_rxd	out std_logic_vector ( 7 downto 0 )
gmii_rx_dv	out std_logic
gmii_rx_er	out std_logic
gmii_isolate	out std_logic
configuration_vector	in std_logic_vector ( 4 downto 0 )
status_vector	out std_logic_vector ( 15 downto 0 )
reset	in std_logic
signal_detect	in std_logic

Member Data Documentation

configuration_vector

configuration_vector in std_logic_vector ( 4 downto 0 )

Port

drpaddr_in

drpaddr_in in std_logic_vector ( 8 downto 0 )

Port

drpclk_in

drpclk_in in std_logic

Port

drpdi_in

drpdi_in in std_logic_vector ( 15 downto 0 )

Port

drpdo_out

drpdo_out out std_logic_vector ( 15 downto 0 )

Port

drpen_in

drpen_in in std_logic

Port

drprdy_out

drprdy_out out std_logic

Port

drpwe_in

drpwe_in in std_logic

Port

EXAMPLE_SIMULATION

EXAMPLE_SIMULATION integer := 0

Generic

gmii_isolate

gmii_isolate out std_logic

Port

gmii_rx_dv

gmii_rx_dv out std_logic

Port

gmii_rx_er

gmii_rx_er out std_logic

Port

gmii_rxd

gmii_rxd out std_logic_vector ( 7 downto 0 )

Port

gmii_tx_en

gmii_tx_en in std_logic

Port

gmii_tx_er

gmii_tx_er in std_logic

Port

gmii_txd

gmii_txd in std_logic_vector ( 7 downto 0 )

Port

gtrefclk

gtrefclk in std_logic

Port

ieee

ieee

Library

independent_clock_bufg

independent_clock_bufg in std_logic

Port

mmcm_locked

mmcm_locked in std_logic

Port

pma_reset

pma_reset in std_logic

Port

reset

reset in std_logic

Port

resetdone

resetdone out std_logic

Port

rxn

rxn in std_logic

Port

rxp

rxp in std_logic

Port

signal_detect

signal_detect in std_logic

Port

status_vector

status_vector out std_logic_vector ( 15 downto 0 )

Port

std_logic_1164

std_logic_1164

Package

txn

txn out std_logic

Port

txoutclk

txoutclk out std_logic

Port

txp

txp out std_logic

Port

unisim

unisim

Library

userclk

userclk in std_logic

Port

userclk2

userclk2 in std_logic

Port

vcomponents

vcomponents

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_block.vhd