gig_eth_pcs_pma_v11_5_example_design Entity Reference

Inheritance diagram for gig_eth_pcs_pma_v11_5_example_design:

Collaboration diagram for gig_eth_pcs_pma_v11_5_example_design:

Entities
top_level	architecture

Libraries
unisim
ieee

Use Clauses
vcomponents
std_logic_1164

Ports
independent_clock	in std_logic
gtrefclk_p	in std_logic
gtrefclk_n	in std_logic
txp	out std_logic
txn	out std_logic
rxp	in std_logic
rxn	in std_logic
gmii_tx_clk	in std_logic
gmii_rx_clk	out std_logic
gmii_txd	in std_logic_vector ( 7 downto 0 )
gmii_tx_en	in std_logic
gmii_tx_er	in std_logic
gmii_rxd	out std_logic_vector ( 7 downto 0 )
gmii_rx_dv	out std_logic
gmii_rx_er	out std_logic
configuration_vector	in std_logic_vector ( 4 downto 0 )
status_vector	out std_logic_vector ( 15 downto 0 )
reset	in std_logic
signal_detect	in std_logic

Member Data Documentation

configuration_vector

configuration_vector in std_logic_vector ( 4 downto 0 )

Port

gmii_rx_clk

gmii_rx_clk out std_logic

Port

gmii_rx_dv

gmii_rx_dv out std_logic

Port

gmii_rx_er

gmii_rx_er out std_logic

Port

gmii_rxd

gmii_rxd out std_logic_vector ( 7 downto 0 )

Port

gmii_tx_clk

gmii_tx_clk in std_logic

Port

gmii_tx_en

gmii_tx_en in std_logic

Port

gmii_tx_er

gmii_tx_er in std_logic

Port

gmii_txd

gmii_txd in std_logic_vector ( 7 downto 0 )

Port

gtrefclk_n

gtrefclk_n in std_logic

Port

gtrefclk_p

gtrefclk_p in std_logic

Port

ieee

ieee

Library

independent_clock

independent_clock in std_logic

Port

reset

reset in std_logic

Port

rxn

rxn in std_logic

Port

rxp

rxp in std_logic

Port

signal_detect

signal_detect in std_logic

Port

status_vector

status_vector out std_logic_vector ( 15 downto 0 )

Port

std_logic_1164

std_logic_1164

Package

txn

txn out std_logic

Port

txp

txp out std_logic

Port

unisim

unisim

Library

vcomponents

vcomponents

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_example_design.vhd