gig_eth_pcs_pma_v11_5_tx_elastic_buffer Entity Reference

Inheritance diagram for gig_eth_pcs_pma_v11_5_tx_elastic_buffer:

Collaboration diagram for gig_eth_pcs_pma_v11_5_tx_elastic_buffer:

Entities
rtl	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
numeric_std
vcomponents

Ports
reset	in std_logic
gmii_tx_clk_wr	in std_logic
gmii_txd_wr	in std_logic_vector ( 7 downto 0 )
gmii_tx_en_wr	in std_logic
gmii_tx_er_wr	in std_logic
gmii_tx_clk_rd	in std_logic
gmii_txd_rd	out std_logic_vector ( 7 downto 0 )
gmii_tx_en_rd	out std_logic
gmii_tx_er_rd	out std_logic

Member Data Documentation

gmii_tx_clk_rd

gmii_tx_clk_rd in std_logic

Port

gmii_tx_clk_wr

gmii_tx_clk_wr in std_logic

Port

gmii_tx_en_rd

gmii_tx_en_rd out std_logic

Port

gmii_tx_en_wr

gmii_tx_en_wr in std_logic

Port

gmii_tx_er_rd

gmii_tx_er_rd out std_logic

Port

gmii_tx_er_wr

gmii_tx_er_wr in std_logic

Port

gmii_txd_rd

gmii_txd_rd out std_logic_vector ( 7 downto 0 )

Port

gmii_txd_wr

gmii_txd_wr in std_logic_vector ( 7 downto 0 )

Port

ieee

ieee

Library

numeric_std

numeric_std

Package

reset

reset in std_logic

Port

std_logic_1164

std_logic_1164

Package

unisim

unisim

Library

vcomponents

vcomponents

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_tx_elastic_buffer.vhd