RTL Architecture Reference

Functions
integer	get_max_wait_bypass ( manual_mode: in in boolean )
integer	get_max_wait_bypass ( manual_mode: in in boolean )

Processes
PROCESS_156	( STABLE_CLOCK )
timeouts	( STABLE_CLOCK )
mmcm_lock_wait	( TXUSERCLK )
reclocking	( STABLE_CLOCK )
PROCESS_157	( TXUSERCLK )
PROCESS_158	( STABLE_CLOCK )
timeout_buffer_bypass	( TXUSERCLK )
reset_fsm	( STABLE_CLOCK )
PROCESS_717	( STABLE_CLOCK )
timeouts	( STABLE_CLOCK )
mmcm_lock_wait	( TXUSERCLK )
reclocking	( STABLE_CLOCK )
PROCESS_718	( TXUSERCLK )
PROCESS_719	( STABLE_CLOCK )
timeout_buffer_bypass	( TXUSERCLK )
reset_fsm	( STABLE_CLOCK )

Constants
MMCM_LOCK_CNT_MAX	integer := 1024
STARTUP_DELAY	integer := 500
WAIT_CYCLES	integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD
WAIT_MAX	integer := WAIT_CYCLES + 10
WAIT_TIMEOUT_2ms	integer := 2000000 / STABLE_CLOCK_PERIOD
WAIT_TLOCK_MAX	integer := 100000 / STABLE_CLOCK_PERIOD
WAIT_TIMEOUT_500us	integer := 500000 / STABLE_CLOCK_PERIOD
MAX_RETRIES	integer := 2 ** RETRY_COUNTER_BITWIDTH - 1
MAX_WAIT_BYPASS	integer := get_max_wait_bypass ( PHASE_ALIGNMENT_MANUAL )

Types
tx_rst_fsm_type	( INIT , ASSERT_ALL_RESETS , RELEASE_PLL_RESET , RELEASE_MMCM_RESET , WAIT_RESET_DONE , DO_PHASE_ALIGNMENT , RESET_FSM_DONE )

Signals
tx_state	tx_rst_fsm_type := INIT
init_wait_count	integer range 0 to WAIT_MAX := 0
init_wait_done	std_logic := ' 0 '
pll_reset_asserted	std_logic := ' 0 '
tx_fsm_reset_done_int	std_logic := ' 0 '
tx_fsm_reset_done_int_s1	std_logic := ' 0 '
tx_fsm_reset_done_int_s2	std_logic := ' 0 '
tx_fsm_reset_done_int_s3	std_logic := ' 0 '
txresetdone_s1	std_logic := ' 0 '
txresetdone_s2	std_logic := ' 0 '
txresetdone_s3	std_logic := ' 0 '
retry_counter_int	integer range 0 to MAX_RETRIES
time_out_counter	integer range 0 to WAIT_TIMEOUT_2ms := 0
reset_time_out	std_logic := ' 0 '
time_out_2ms	std_logic := ' 0 '
time_tlock_max	std_logic := ' 0 '
time_out_500us	std_logic := ' 0 '
mmcm_lock_count	integer range 0 to MMCM_LOCK_CNT_MAX - 1 := 0
mmcm_lock_int	std_logic := ' 0 '
mmcm_lock_reclocked	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
run_phase_alignment_int	std_logic := ' 0 '
run_phase_alignment_int_s1	std_logic := ' 0 '
run_phase_alignment_int_s2	std_logic := ' 0 '
run_phase_alignment_int_s3	std_logic := ' 0 '
wait_bypass_count	integer range 0 to MAX_WAIT_BYPASS - 1
time_out_wait_bypass	std_logic := ' 0 '
time_out_wait_bypass_s1	std_logic := ' 0 '
time_out_wait_bypass_s2	std_logic := ' 0 '
time_out_wait_bypass_s3	std_logic := ' 0 '
refclk_lost	std_logic

Member Function Documentation

get_max_wait_bypass() [1/2]

integer get_max_wait_bypass (   manual_mode in in boolean   )

Function

get_max_wait_bypass() [2/2]

integer get_max_wait_bypass (   manual_mode in in boolean   )

Function

mmcm_lock_wait() [1/2]

mmcm_lock_wait (   TXUSERCLK   )

Process

mmcm_lock_wait() [2/2]

mmcm_lock_wait (   TXUSERCLK   )

Process

PROCESS_156()

PROCESS_156 (   STABLE_CLOCK   )

Process

PROCESS_157()

PROCESS_157 (   TXUSERCLK   )

Process

PROCESS_158()

PROCESS_158 (   STABLE_CLOCK   )

Process

PROCESS_717()

PROCESS_717 (   STABLE_CLOCK   )

Process

PROCESS_718()

PROCESS_718 (   TXUSERCLK   )

Process

PROCESS_719()

PROCESS_719 (   STABLE_CLOCK   )

Process

reclocking() [1/2]

reclocking (   STABLE_CLOCK   )

Process

reclocking() [2/2]

reclocking (   STABLE_CLOCK   )

Process

reset_fsm() [1/2]

reset_fsm (   STABLE_CLOCK   )

Process

reset_fsm() [2/2]

reset_fsm (   STABLE_CLOCK   )

Process

timeout_buffer_bypass() [1/2]

timeout_buffer_bypass (   TXUSERCLK   )

Process

timeout_buffer_bypass() [2/2]

timeout_buffer_bypass (   TXUSERCLK   )

Process

timeouts() [1/2]

timeouts (   STABLE_CLOCK   )

Process

timeouts() [2/2]

timeouts (   STABLE_CLOCK   )

Process

Member Data Documentation

init_wait_count

init_wait_count integer range 0 to WAIT_MAX := 0

Signal

init_wait_done

init_wait_done std_logic := ' 0 '

Signal

MAX_RETRIES

MAX_RETRIES integer := 2 ** RETRY_COUNTER_BITWIDTH - 1

Constant

MAX_WAIT_BYPASS

MAX_WAIT_BYPASS integer := get_max_wait_bypass ( PHASE_ALIGNMENT_MANUAL )

Constant

MMCM_LOCK_CNT_MAX

MMCM_LOCK_CNT_MAX integer := 1024

Constant

mmcm_lock_count

mmcm_lock_count integer range 0 to MMCM_LOCK_CNT_MAX - 1 := 0

Signal

mmcm_lock_int

mmcm_lock_int std_logic := ' 0 '

Signal

mmcm_lock_reclocked

mmcm_lock_reclocked std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Signal

pll_reset_asserted

pll_reset_asserted std_logic := ' 0 '

Signal

refclk_lost

refclk_lost std_logic

Signal

reset_time_out

reset_time_out std_logic := ' 0 '

Signal

retry_counter_int

retry_counter_int integer range 0 to MAX_RETRIES

Signal

run_phase_alignment_int

run_phase_alignment_int std_logic := ' 0 '

Signal

run_phase_alignment_int_s1

run_phase_alignment_int_s1 std_logic := ' 0 '

Signal

run_phase_alignment_int_s2

run_phase_alignment_int_s2 std_logic := ' 0 '

Signal

run_phase_alignment_int_s3

run_phase_alignment_int_s3 std_logic := ' 0 '

Signal

STARTUP_DELAY

STARTUP_DELAY integer := 500

Constant

time_out_2ms

time_out_2ms std_logic := ' 0 '

Signal

time_out_500us

time_out_500us std_logic := ' 0 '

Signal

time_out_counter

time_out_counter integer range 0 to WAIT_TIMEOUT_2ms := 0

Signal

time_out_wait_bypass

time_out_wait_bypass std_logic := ' 0 '

Signal

time_out_wait_bypass_s1

time_out_wait_bypass_s1 std_logic := ' 0 '

Signal

time_out_wait_bypass_s2

time_out_wait_bypass_s2 std_logic := ' 0 '

Signal

time_out_wait_bypass_s3

time_out_wait_bypass_s3 std_logic := ' 0 '

Signal

time_tlock_max

time_tlock_max std_logic := ' 0 '

Signal

tx_fsm_reset_done_int

tx_fsm_reset_done_int std_logic := ' 0 '

Signal

tx_fsm_reset_done_int_s1

tx_fsm_reset_done_int_s1 std_logic := ' 0 '

Signal

tx_fsm_reset_done_int_s2

tx_fsm_reset_done_int_s2 std_logic := ' 0 '

Signal

tx_fsm_reset_done_int_s3

tx_fsm_reset_done_int_s3 std_logic := ' 0 '

Signal

tx_rst_fsm_type

tx_rst_fsm_type ( INIT , ASSERT_ALL_RESETS , RELEASE_PLL_RESET , RELEASE_MMCM_RESET , WAIT_RESET_DONE , DO_PHASE_ALIGNMENT , RESET_FSM_DONE )

Type

tx_state

tx_state tx_rst_fsm_type := INIT

Signal

txresetdone_s1

txresetdone_s1 std_logic := ' 0 '

Signal

txresetdone_s2

txresetdone_s2 std_logic := ' 0 '

Signal

txresetdone_s3

txresetdone_s3 std_logic := ' 0 '

Signal

wait_bypass_count

wait_bypass_count integer range 0 to MAX_WAIT_BYPASS - 1

Signal

WAIT_CYCLES

WAIT_CYCLES integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD

Constant

WAIT_MAX

WAIT_MAX integer := WAIT_CYCLES + 10

Constant

WAIT_TIMEOUT_2ms

WAIT_TIMEOUT_2ms integer := 2000000 / STABLE_CLOCK_PERIOD

Constant

WAIT_TIMEOUT_500us

WAIT_TIMEOUT_500us integer := 500000 / STABLE_CLOCK_PERIOD

Constant

WAIT_TLOCK_MAX

WAIT_TLOCK_MAX integer := 100000 / STABLE_CLOCK_PERIOD

Constant

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe_tx_startup_fsm.vhd