gtwizard_v2_3_gbe_gth_init Entity Reference

Inheritance diagram for gtwizard_v2_3_gbe_gth_init:

Collaboration diagram for gtwizard_v2_3_gbe_gth_init:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
std_logic_unsigned
VCOMPONENTS

Generics
EXAMPLE_SIM_GTRESET_SPEEDUP	string := " TRUE "
EXAMPLE_SIMULATION	integer := 0
EXAMPLE_USE_CHIPSCOPE	integer := 0

Ports
SYSCLK_IN	in std_logic
SOFT_RESET_IN	in std_logic
GT0_TX_FSM_RESET_DONE_OUT	out std_logic
GT0_RX_FSM_RESET_DONE_OUT	out std_logic
GT0_DATA_VALID_IN	in std_logic
GT0_GTREFCLK0_IN	in std_logic
GT0_CPLLFBCLKLOST_OUT	out std_logic
GT0_CPLLLOCK_OUT	out std_logic
GT0_CPLLLOCKDETCLK_IN	in std_logic
GT0_CPLLRESET_IN	in std_logic
GT0_EYESCANDATAERROR_OUT	out std_logic
GT0_LOOPBACK_IN	in std_logic_vector ( 2 downto 0 )
GT0_RXPD_IN	in std_logic_vector ( 1 downto 0 )
GT0_TXPD_IN	in std_logic_vector ( 1 downto 0 )
GT0_RXUSERRDY_IN	in std_logic
GT0_RXCHARISCOMMA_OUT	out std_logic_vector ( 1 downto 0 )
GT0_RXCHARISK_OUT	out std_logic_vector ( 1 downto 0 )
GT0_RXDISPERR_OUT	out std_logic_vector ( 1 downto 0 )
GT0_RXNOTINTABLE_OUT	out std_logic_vector ( 1 downto 0 )
GT0_RXCLKCORCNT_OUT	out std_logic_vector ( 1 downto 0 )
GT0_RXMCOMMAALIGNEN_IN	in std_logic
GT0_RXPCOMMAALIGNEN_IN	in std_logic
GT0_GTRXRESET_IN	in std_logic
GT0_RXDATA_OUT	out std_logic_vector ( 15 downto 0 )
GT0_RXOUTCLK_OUT	out std_logic
GT0_RXUSRCLK_IN	in std_logic
GT0_RXUSRCLK2_IN	in std_logic
GT0_RXMONITOROUT_OUT	out std_logic_vector ( 6 downto 0 )
GT0_RXMONITORSEL_IN	in std_logic_vector ( 1 downto 0 )
GT0_GTHRXN_IN	in std_logic
GT0_GTHRXP_IN	in std_logic
GT0_RXCDRLOCK_OUT	out std_logic
GT0_RXELECIDLE_OUT	out std_logic
GT0_RXBUFRESET_IN	in std_logic
GT0_RXBUFSTATUS_OUT	out std_logic_vector ( 2 downto 0 )
GT0_RXRESETDONE_OUT	out std_logic
GT0_TXUSERRDY_IN	in std_logic
GT0_TXCHARDISPMODE_IN	in std_logic_vector ( 1 downto 0 )
GT0_TXCHARDISPVAL_IN	in std_logic_vector ( 1 downto 0 )
GT0_TXCHARISK_IN	in std_logic_vector ( 1 downto 0 )
GT0_TXBUFSTATUS_OUT	out std_logic_vector ( 1 downto 0 )
GT0_GTTXRESET_IN	in std_logic
GT0_TXDATA_IN	in std_logic_vector ( 15 downto 0 )
GT0_TXOUTCLK_OUT	out std_logic
GT0_TXOUTCLKFABRIC_OUT	out std_logic
GT0_TXOUTCLKPCS_OUT	out std_logic
GT0_TXUSRCLK_IN	in std_logic
GT0_TXUSRCLK2_IN	in std_logic
GT0_GTHTXN_OUT	out std_logic
GT0_GTHTXP_OUT	out std_logic
GT0_TXRESETDONE_OUT	out std_logic
GT0_GTREFCLK0_COMMON_IN	in std_logic
GT0_QPLLLOCK_OUT	out std_logic
GT0_QPLLLOCKDETCLK_IN	in std_logic
GT0_QPLLRESET_IN	in std_logic
mmcm_lock	in std_logic
mmcm_reset	out std_logic

Member Data Documentation

EXAMPLE_SIM_GTRESET_SPEEDUP

EXAMPLE_SIM_GTRESET_SPEEDUP string := " TRUE "

Generic

EXAMPLE_SIMULATION

EXAMPLE_SIMULATION integer := 0

Generic

EXAMPLE_USE_CHIPSCOPE

EXAMPLE_USE_CHIPSCOPE integer := 0

Generic

GT0_CPLLFBCLKLOST_OUT

GT0_CPLLFBCLKLOST_OUT out std_logic

Port

GT0_CPLLLOCK_OUT

GT0_CPLLLOCK_OUT out std_logic

Port

GT0_CPLLLOCKDETCLK_IN

GT0_CPLLLOCKDETCLK_IN in std_logic

Port

GT0_CPLLRESET_IN

GT0_CPLLRESET_IN in std_logic

Port

GT0_DATA_VALID_IN

GT0_DATA_VALID_IN in std_logic

Port

GT0_EYESCANDATAERROR_OUT

GT0_EYESCANDATAERROR_OUT out std_logic

Port

GT0_GTHRXN_IN

GT0_GTHRXN_IN in std_logic

Port

GT0_GTHRXP_IN

GT0_GTHRXP_IN in std_logic

Port

GT0_GTHTXN_OUT

GT0_GTHTXN_OUT out std_logic

Port

GT0_GTHTXP_OUT

GT0_GTHTXP_OUT out std_logic

Port

GT0_GTREFCLK0_COMMON_IN

GT0_GTREFCLK0_COMMON_IN in std_logic

Port

GT0_GTREFCLK0_IN

GT0_GTREFCLK0_IN in std_logic

Port

GT0_GTRXRESET_IN

GT0_GTRXRESET_IN in std_logic

Port

GT0_GTTXRESET_IN

GT0_GTTXRESET_IN in std_logic

Port

GT0_LOOPBACK_IN

GT0_LOOPBACK_IN in std_logic_vector ( 2 downto 0 )

Port

GT0_QPLLLOCK_OUT

GT0_QPLLLOCK_OUT out std_logic

Port

GT0_QPLLLOCKDETCLK_IN

GT0_QPLLLOCKDETCLK_IN in std_logic

Port

GT0_QPLLRESET_IN

GT0_QPLLRESET_IN in std_logic

Port

GT0_RX_FSM_RESET_DONE_OUT

GT0_RX_FSM_RESET_DONE_OUT out std_logic

Port

GT0_RXBUFRESET_IN

GT0_RXBUFRESET_IN in std_logic

Port

GT0_RXBUFSTATUS_OUT

GT0_RXBUFSTATUS_OUT out std_logic_vector ( 2 downto 0 )

Port

GT0_RXCDRLOCK_OUT

GT0_RXCDRLOCK_OUT out std_logic

Port

GT0_RXCHARISCOMMA_OUT

GT0_RXCHARISCOMMA_OUT out std_logic_vector ( 1 downto 0 )

Port

GT0_RXCHARISK_OUT

GT0_RXCHARISK_OUT out std_logic_vector ( 1 downto 0 )

Port

GT0_RXCLKCORCNT_OUT

GT0_RXCLKCORCNT_OUT out std_logic_vector ( 1 downto 0 )

Port

GT0_RXDATA_OUT

GT0_RXDATA_OUT out std_logic_vector ( 15 downto 0 )

Port

GT0_RXDISPERR_OUT

GT0_RXDISPERR_OUT out std_logic_vector ( 1 downto 0 )

Port

GT0_RXELECIDLE_OUT

GT0_RXELECIDLE_OUT out std_logic

Port

GT0_RXMCOMMAALIGNEN_IN

GT0_RXMCOMMAALIGNEN_IN in std_logic

Port

GT0_RXMONITOROUT_OUT

GT0_RXMONITOROUT_OUT out std_logic_vector ( 6 downto 0 )

Port

GT0_RXMONITORSEL_IN

GT0_RXMONITORSEL_IN in std_logic_vector ( 1 downto 0 )

Port

GT0_RXNOTINTABLE_OUT

GT0_RXNOTINTABLE_OUT out std_logic_vector ( 1 downto 0 )

Port

GT0_RXOUTCLK_OUT

GT0_RXOUTCLK_OUT out std_logic

Port

GT0_RXPCOMMAALIGNEN_IN

GT0_RXPCOMMAALIGNEN_IN in std_logic

Port

GT0_RXPD_IN

GT0_RXPD_IN in std_logic_vector ( 1 downto 0 )

Port

GT0_RXRESETDONE_OUT

GT0_RXRESETDONE_OUT out std_logic

Port

GT0_RXUSERRDY_IN

GT0_RXUSERRDY_IN in std_logic

Port

GT0_RXUSRCLK2_IN

GT0_RXUSRCLK2_IN in std_logic

Port

GT0_RXUSRCLK_IN

GT0_RXUSRCLK_IN in std_logic

Port

GT0_TX_FSM_RESET_DONE_OUT

GT0_TX_FSM_RESET_DONE_OUT out std_logic

Port

GT0_TXBUFSTATUS_OUT

GT0_TXBUFSTATUS_OUT out std_logic_vector ( 1 downto 0 )

Port

GT0_TXCHARDISPMODE_IN

GT0_TXCHARDISPMODE_IN in std_logic_vector ( 1 downto 0 )

Port

GT0_TXCHARDISPVAL_IN

GT0_TXCHARDISPVAL_IN in std_logic_vector ( 1 downto 0 )

Port

GT0_TXCHARISK_IN

GT0_TXCHARISK_IN in std_logic_vector ( 1 downto 0 )

Port

GT0_TXDATA_IN

GT0_TXDATA_IN in std_logic_vector ( 15 downto 0 )

Port

GT0_TXOUTCLK_OUT

GT0_TXOUTCLK_OUT out std_logic

Port

GT0_TXOUTCLKFABRIC_OUT

GT0_TXOUTCLKFABRIC_OUT out std_logic

Port

GT0_TXOUTCLKPCS_OUT

GT0_TXOUTCLKPCS_OUT out std_logic

Port

GT0_TXPD_IN

GT0_TXPD_IN in std_logic_vector ( 1 downto 0 )

Port

GT0_TXRESETDONE_OUT

GT0_TXRESETDONE_OUT out std_logic

Port

GT0_TXUSERRDY_IN

GT0_TXUSERRDY_IN in std_logic

Port

GT0_TXUSRCLK2_IN

GT0_TXUSRCLK2_IN in std_logic

Port

GT0_TXUSRCLK_IN

GT0_TXUSRCLK_IN in std_logic

Port

ieee

ieee

Library

mmcm_lock

mmcm_lock in std_logic

Port

mmcm_reset

mmcm_reset out std_logic

Port

numeric_std

numeric_std

Package

SOFT_RESET_IN

SOFT_RESET_IN in std_logic

Port

std_logic_1164

std_logic_1164

Package

std_logic_unsigned

std_logic_unsigned

Package

SYSCLK_IN

SYSCLK_IN in std_logic

Port

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gtwizard_v2_3_gbe_gth/gtwizard_v2_3_gbe_gth_init.vhd