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My Project
v0.0.16
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Entities | |
| RTL | architecture |
Libraries | |
| ieee | |
| UNISIM | |
Use Clauses | |
| std_logic_1164 | |
| numeric_std | |
| textio | |
| std_logic_textio | |
| std_logic_unsigned | |
| VCOMPONENTS | |
Generics | |
| RX_DATA_WIDTH | integer := 16 |
| RXCTRL_WIDTH | integer := 2 |
| WORDS_IN_BRAM | integer := 256 |
| CHANBOND_SEQ_LEN | integer := 1 |
| COMMA_DOUBLE | std_logic_vector ( 15 downto 0 ) := x " f628 " |
| START_OF_PACKET_CHAR | std_logic_vector ( 15 downto 0 ) := x " 02bc " |
Ports | |
| RX_DATA_IN | in std_logic_vector ( ( RX_DATA_WIDTH - 1 ) downto 0 ) |
| RXCTRL_IN | in std_logic_vector ( ( RXCTRL_WIDTH - 1 ) downto 0 ) |
| RXENPCOMMADET_OUT | out std_logic |
| RXENMCOMMADET_OUT | out std_logic |
| RX_ENCHAN_SYNC_OUT | out std_logic |
| RX_CHANBOND_SEQ_IN | in std_logic |
| INC_IN | in std_logic |
| INC_OUT | out std_logic |
| PATTERN_MATCHB_OUT | out std_logic |
| RESET_ON_ERROR_IN | in std_logic |
| ERROR_COUNT_OUT | out std_logic_vector ( 7 downto 0 ) |
| TRACK_DATA_OUT | out std_logic |
| USER_CLK | in std_logic |
| SYSTEM_RESET | in std_logic |
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1.8.13