My Project  v0.0.16
Generics | Ports | Libraries | Use Clauses
gtwizard_v2_5_gbe_gth_GT_FRAME_CHECK Entity Reference
Inheritance diagram for gtwizard_v2_5_gbe_gth_GT_FRAME_CHECK:
Inheritance graph
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Entities

RTL  architecture
 

Libraries

ieee 
UNISIM 

Use Clauses

std_logic_1164 
numeric_std 
textio 
std_logic_textio 
std_logic_unsigned 
VCOMPONENTS 

Generics

RX_DATA_WIDTH  integer := 16
RXCTRL_WIDTH  integer := 2
WORDS_IN_BRAM  integer := 256
CHANBOND_SEQ_LEN  integer := 1
COMMA_DOUBLE  std_logic_vector ( 15 downto 0 ) := x " f628 "
START_OF_PACKET_CHAR  std_logic_vector ( 15 downto 0 ) := x " 02bc "

Ports

RX_DATA_IN   in std_logic_vector ( ( RX_DATA_WIDTH - 1 ) downto 0 )
RXCTRL_IN   in std_logic_vector ( ( RXCTRL_WIDTH - 1 ) downto 0 )
RXENPCOMMADET_OUT   out std_logic
RXENMCOMMADET_OUT   out std_logic
RX_ENCHAN_SYNC_OUT   out std_logic
RX_CHANBOND_SEQ_IN   in std_logic
INC_IN   in std_logic
INC_OUT   out std_logic
PATTERN_MATCHB_OUT   out std_logic
RESET_ON_ERROR_IN   in std_logic
ERROR_COUNT_OUT   out std_logic_vector ( 7 downto 0 )
TRACK_DATA_OUT   out std_logic
USER_CLK   in std_logic
SYSTEM_RESET   in std_logic

Member Data Documentation

◆ CHANBOND_SEQ_LEN

CHANBOND_SEQ_LEN integer := 1
Generic

◆ COMMA_DOUBLE

COMMA_DOUBLE std_logic_vector ( 15 downto 0 ) := x " f628 "
Generic

◆ ERROR_COUNT_OUT

ERROR_COUNT_OUT out std_logic_vector ( 7 downto 0 )
Port

◆ ieee

ieee
Library

◆ INC_IN

INC_IN in std_logic
Port

◆ INC_OUT

INC_OUT out std_logic
Port

◆ numeric_std

numeric_std
Package

◆ PATTERN_MATCHB_OUT

PATTERN_MATCHB_OUT out std_logic
Port

◆ RESET_ON_ERROR_IN

RESET_ON_ERROR_IN in std_logic
Port

◆ RX_CHANBOND_SEQ_IN

RX_CHANBOND_SEQ_IN in std_logic
Port

◆ RX_DATA_IN

RX_DATA_IN in std_logic_vector ( ( RX_DATA_WIDTH - 1 ) downto 0 )
Port

◆ RX_DATA_WIDTH

RX_DATA_WIDTH integer := 16
Generic

◆ RX_ENCHAN_SYNC_OUT

RX_ENCHAN_SYNC_OUT out std_logic
Port

◆ RXCTRL_IN

RXCTRL_IN in std_logic_vector ( ( RXCTRL_WIDTH - 1 ) downto 0 )
Port

◆ RXCTRL_WIDTH

RXCTRL_WIDTH integer := 2
Generic

◆ RXENMCOMMADET_OUT

RXENMCOMMADET_OUT out std_logic
Port

◆ RXENPCOMMADET_OUT

RXENPCOMMADET_OUT out std_logic
Port

◆ START_OF_PACKET_CHAR

START_OF_PACKET_CHAR std_logic_vector ( 15 downto 0 ) := x " 02bc "
Generic

◆ std_logic_1164

std_logic_1164
Package

◆ std_logic_textio

◆ std_logic_unsigned

◆ SYSTEM_RESET

SYSTEM_RESET in std_logic
Port

◆ textio

textio
Package

◆ TRACK_DATA_OUT

TRACK_DATA_OUT out std_logic
Port

◆ UNISIM

UNISIM
Library

◆ USER_CLK

USER_CLK in std_logic
Port

◆ VCOMPONENTS

VCOMPONENTS
Package

◆ WORDS_IN_BRAM

WORDS_IN_BRAM integer := 256
Generic

The documentation for this class was generated from the following file: