gtwizard_v2_5_gbe_gth_GT_USRCLK_SOURCE Entity Reference

Inheritance diagram for gtwizard_v2_5_gbe_gth_GT_USRCLK_SOURCE:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
std_logic_unsigned
VCOMPONENTS

Ports
Q9_CLK0_GTREFCLK_PAD_N_IN	in std_logic
Q9_CLK0_GTREFCLK_PAD_P_IN	in std_logic
Q9_CLK0_GTREFCLK_OUT	out std_logic
GT0_TXUSRCLK_OUT	out std_logic
GT0_TXUSRCLK2_OUT	out std_logic
GT0_TXOUTCLK_IN	in std_logic
GT0_RXUSRCLK_OUT	out std_logic
GT0_RXUSRCLK2_OUT	out std_logic
GT0_RXOUTCLK_IN	in std_logic
DRPCLK_IN	in std_logic
DRPCLK_OUT	out std_logic

Member Data Documentation

DRPCLK_IN

DRPCLK_IN in std_logic

Port

DRPCLK_OUT

DRPCLK_OUT out std_logic

Port

GT0_RXOUTCLK_IN

GT0_RXOUTCLK_IN in std_logic

Port

GT0_RXUSRCLK2_OUT

GT0_RXUSRCLK2_OUT out std_logic

Port

GT0_RXUSRCLK_OUT

GT0_RXUSRCLK_OUT out std_logic

Port

GT0_TXOUTCLK_IN

GT0_TXOUTCLK_IN in std_logic

Port

GT0_TXUSRCLK2_OUT

GT0_TXUSRCLK2_OUT out std_logic

Port

GT0_TXUSRCLK_OUT

GT0_TXUSRCLK_OUT out std_logic

Port

ieee

ieee

Library

numeric_std

numeric_std

Package

Q9_CLK0_GTREFCLK_OUT

Q9_CLK0_GTREFCLK_OUT out std_logic

Port

Q9_CLK0_GTREFCLK_PAD_N_IN

Q9_CLK0_GTREFCLK_PAD_N_IN in std_logic

Port

Q9_CLK0_GTREFCLK_PAD_P_IN

Q9_CLK0_GTREFCLK_PAD_P_IN in std_logic

Port

std_logic_1164

std_logic_1164

Package

std_logic_unsigned

std_logic_unsigned

Package

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gtwizard_v2_5_gbe_gth/gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_gt_usrclk_source.vhd