gtwizard_v2_5_gbe_gth_rxrate_seq Entity Reference

Inheritance diagram for gtwizard_v2_5_gbe_gth_rxrate_seq:

Collaboration diagram for gtwizard_v2_5_gbe_gth_rxrate_seq:

Entities
Behavioral	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Ports
RST	in std_logic
RXRATE_IN	in std_logic_vector ( 2 downto 0 )
RXPMARESETDONE	in std_logic
RXRATE_OUT	out std_logic_vector ( 2 downto 0 )
DRPCLK	in std_logic
DRPADDR	out std_logic_vector ( 8 downto 0 )
DRPDO	in std_logic_vector ( 15 downto 0 )
DRPDI	out std_logic_vector ( 15 downto 0 )
DRPRDY	in std_logic
DRPEN	out std_logic
DRPWE	out std_logic
DRP_BUSY_IN	in std_logic
DRP_RATE_BUSY_OUT	out std_logic

Member Data Documentation

DRP_BUSY_IN

DRP_BUSY_IN in std_logic

Port

DRP_RATE_BUSY_OUT

DRP_RATE_BUSY_OUT out std_logic

Port

DRPADDR

DRPADDR out std_logic_vector ( 8 downto 0 )

Port

DRPCLK

DRPCLK in std_logic

Port

DRPDI

DRPDI out std_logic_vector ( 15 downto 0 )

Port

DRPDO

DRPDO in std_logic_vector ( 15 downto 0 )

Port

DRPEN

DRPEN out std_logic

Port

DRPRDY

DRPRDY in std_logic

Port

DRPWE

DRPWE out std_logic

Port

ieee

ieee

Library

numeric_std

numeric_std

Package

RST

RST in std_logic

Port

RXPMARESETDONE

RXPMARESETDONE in std_logic

Port

RXRATE_IN

RXRATE_IN in std_logic_vector ( 2 downto 0 )

Port

RXRATE_OUT

RXRATE_OUT out std_logic_vector ( 2 downto 0 )

Port

std_logic_1164

std_logic_1164

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gtwizard_v2_5_gbe_gth/gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_rxrate_seq.vhd