arch Architecture Reference

Processes
PROCESS_368	( clk )
PROCESS_369	( clk , nReset )
PROCESS_370	( clk , nReset )
PROCESS_371	( clk , nReset )
PROCESS_372	( clk , nReset )
PROCESS_373	( clk , nReset )
PROCESS_374	( clk , nReset )
PROCESS_375	( clk )
PROCESS_376	( clk , nReset )
PROCESS_930	( clk )
PROCESS_931	( clk , nReset )
PROCESS_932	( clk , nReset )
PROCESS_933	( clk , nReset )
PROCESS_934	( clk , nReset )
PROCESS_935	( clk , nReset )
PROCESS_936	( clk , nReset )
PROCESS_937	( clk )
PROCESS_938	( clk , nReset )

Constants
idle	std_logic_vector ( 16 downto 0 ) := " 00000000000000000 "
start_a	std_logic_vector ( 16 downto 0 ) := " 00000000000000001 "
start_b	std_logic_vector ( 16 downto 0 ) := " 00000000000000010 "
start_c	std_logic_vector ( 16 downto 0 ) := " 00000000000000100 "
start_d	std_logic_vector ( 16 downto 0 ) := " 00000000000001000 "
start_e	std_logic_vector ( 16 downto 0 ) := " 00000000000010000 "
stop_a	std_logic_vector ( 16 downto 0 ) := " 00000000000100000 "
stop_b	std_logic_vector ( 16 downto 0 ) := " 00000000001000000 "
stop_c	std_logic_vector ( 16 downto 0 ) := " 00000000010000000 "
stop_d	std_logic_vector ( 16 downto 0 ) := " 00000000100000000 "
rd_a	std_logic_vector ( 16 downto 0 ) := " 00000001000000000 "
rd_b	std_logic_vector ( 16 downto 0 ) := " 00000010000000000 "
rd_c	std_logic_vector ( 16 downto 0 ) := " 00000100000000000 "
rd_d	std_logic_vector ( 16 downto 0 ) := " 00001000000000000 "
wr_a	std_logic_vector ( 16 downto 0 ) := " 00010000000000000 "
wr_b	std_logic_vector ( 16 downto 0 ) := " 00100000000000000 "
wr_c	std_logic_vector ( 16 downto 0 ) := " 01000000000000000 "
wr_d	std_logic_vector ( 16 downto 0 ) := " 10000000000000000 "
I2C_CMD_NOP	std_logic_vector ( 3 downto 0 ) := " 0000 "
I2C_CMD_START	std_logic_vector ( 3 downto 0 ) := " 0001 "
I2C_CMD_STOP	std_logic_vector ( 3 downto 0 ) := " 0010 "
I2C_CMD_WRITE	std_logic_vector ( 3 downto 0 ) := " 0100 "
I2C_CMD_READ	std_logic_vector ( 3 downto 0 ) := " 1000 "

Signals
sSCL	std_logic
sSDA	std_logic
dscl_oen	std_logic
sda_chk	std_logic
clk_en	std_logic
slave_wait	std_logic
dSCL	std_logic
dSDA	std_logic
sta_condition	std_logic
sto_condition	std_logic
cmd_stop	std_logic
cnt	std_logic_vector ( 15 downto 0 )
scl_oen_int	std_logic
sda_oen_int	std_logic
busy_int	std_logic
al_int	std_logic
c_state	std_logic_vector ( 16 downto 0 )

Member Function Documentation

PROCESS_368()

PROCESS_368 (   clk   )

Process

PROCESS_369()

PROCESS_369 (   clk ,   nReset   )

Process

PROCESS_370()

PROCESS_370 (   clk ,   nReset   )

Process

PROCESS_371()

PROCESS_371 (   clk ,   nReset   )

Process

PROCESS_372()

PROCESS_372 (   clk ,   nReset   )

Process

PROCESS_373()

PROCESS_373 (   clk ,   nReset   )

Process

PROCESS_374()

PROCESS_374 (   clk ,   nReset   )

Process

PROCESS_375()

PROCESS_375 (   clk   )

Process

PROCESS_376()

PROCESS_376 (   clk ,   nReset   )

Process

PROCESS_930()

PROCESS_930 (   clk   )

Process

PROCESS_931()

PROCESS_931 (   clk ,   nReset   )

Process

PROCESS_932()

PROCESS_932 (   clk ,   nReset   )

Process

PROCESS_933()

PROCESS_933 (   clk ,   nReset   )

Process

PROCESS_934()

PROCESS_934 (   clk ,   nReset   )

Process

PROCESS_935()

PROCESS_935 (   clk ,   nReset   )

Process

PROCESS_936()

PROCESS_936 (   clk ,   nReset   )

Process

PROCESS_937()

PROCESS_937 (   clk   )

Process

PROCESS_938()

PROCESS_938 (   clk ,   nReset   )

Process

Member Data Documentation

al_int

al_int std_logic

Signal

busy_int

busy_int std_logic

Signal

c_state

c_state std_logic_vector ( 16 downto 0 )

Signal

clk_en

clk_en std_logic

Signal

cmd_stop

cmd_stop std_logic

Signal

cnt

cnt std_logic_vector ( 15 downto 0 )

Signal

dSCL

dSCL std_logic

Signal

dscl_oen

dscl_oen std_logic

Signal

dSDA

dSDA std_logic

Signal

I2C_CMD_NOP

I2C_CMD_NOP std_logic_vector ( 3 downto 0 ) := " 0000 "

Constant

I2C_CMD_READ

I2C_CMD_READ std_logic_vector ( 3 downto 0 ) := " 1000 "

Constant

I2C_CMD_START

I2C_CMD_START std_logic_vector ( 3 downto 0 ) := " 0001 "

Constant

I2C_CMD_STOP

I2C_CMD_STOP std_logic_vector ( 3 downto 0 ) := " 0010 "

Constant

I2C_CMD_WRITE

I2C_CMD_WRITE std_logic_vector ( 3 downto 0 ) := " 0100 "

Constant

idle

idle std_logic_vector ( 16 downto 0 ) := " 00000000000000000 "

Constant

rd_a

rd_a std_logic_vector ( 16 downto 0 ) := " 00000001000000000 "

Constant

rd_b

rd_b std_logic_vector ( 16 downto 0 ) := " 00000010000000000 "

Constant

rd_c

rd_c std_logic_vector ( 16 downto 0 ) := " 00000100000000000 "

Constant

rd_d

rd_d std_logic_vector ( 16 downto 0 ) := " 00001000000000000 "

Constant

scl_oen_int

scl_oen_int std_logic

Signal

sda_chk

sda_chk std_logic

Signal

sda_oen_int

sda_oen_int std_logic

Signal

slave_wait

slave_wait std_logic

Signal

sSCL

sSCL std_logic

Signal

sSDA

sSDA std_logic

Signal

sta_condition

sta_condition std_logic

Signal

start_a

start_a std_logic_vector ( 16 downto 0 ) := " 00000000000000001 "

Constant

start_b

start_b std_logic_vector ( 16 downto 0 ) := " 00000000000000010 "

Constant

start_c

start_c std_logic_vector ( 16 downto 0 ) := " 00000000000000100 "

Constant

start_d

start_d std_logic_vector ( 16 downto 0 ) := " 00000000000001000 "

Constant

start_e

start_e std_logic_vector ( 16 downto 0 ) := " 00000000000010000 "

Constant

sto_condition

sto_condition std_logic

Signal

stop_a

stop_a std_logic_vector ( 16 downto 0 ) := " 00000000000100000 "

Constant

stop_b

stop_b std_logic_vector ( 16 downto 0 ) := " 00000000001000000 "

Constant

stop_c

stop_c std_logic_vector ( 16 downto 0 ) := " 00000000010000000 "

Constant

stop_d

stop_d std_logic_vector ( 16 downto 0 ) := " 00000000100000000 "

Constant

wr_a

wr_a std_logic_vector ( 16 downto 0 ) := " 00010000000000000 "

Constant

wr_b

wr_b std_logic_vector ( 16 downto 0 ) := " 00100000000000000 "

Constant

wr_c

wr_c std_logic_vector ( 16 downto 0 ) := " 01000000000000000 "

Constant

wr_d

wr_d std_logic_vector ( 16 downto 0 ) := " 10000000000000000 "

Constant

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The documentation for this class was generated from the following file:

• components/opencores_i2c/firmware/hdl/i2c_master_bit_ctrl.vhd