i2c_master_registers Entity Reference

Inheritance diagram for i2c_master_registers:

Entities
arch	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned

Ports
wb_clk_i	in std_logic
rst_i	in std_logic
wb_rst_i	in std_logic
wb_dat_i	in std_logic_vector ( 7 downto 0 )
wb_adr_i	in std_logic_vector ( 2 downto 0 )
wb_wacc	in std_logic
i2c_al	in std_logic
i2c_busy	in std_logic
done	in std_logic
irxack	in std_logic
prer	out std_logic_vector ( 15 downto 0 )
ctr	out std_logic_vector ( 7 downto 0 )
txr	out std_logic_vector ( 7 downto 0 )
cr	out std_logic_vector ( 7 downto 0 )
sr	out std_logic_vector ( 7 downto 0 )

Member Data Documentation

cr

cr out std_logic_vector ( 7 downto 0 )

Port

ctr

ctr out std_logic_vector ( 7 downto 0 )

Port

done

done in std_logic

Port

i2c_al

i2c_al in std_logic

Port

i2c_busy

i2c_busy in std_logic

Port

ieee

ieee

Library

irxack

irxack in std_logic

Port

prer

prer out std_logic_vector ( 15 downto 0 )

Port

rst_i

rst_i in std_logic

Port

sr

sr out std_logic_vector ( 7 downto 0 )

Port

std_logic_1164

std_logic_1164

Package

std_logic_arith

std_logic_arith

Package

std_logic_unsigned

std_logic_unsigned

Package

txr

txr out std_logic_vector ( 7 downto 0 )

Port

wb_adr_i

wb_adr_i in std_logic_vector ( 2 downto 0 )

Port

wb_clk_i

wb_clk_i in std_logic

Port

wb_dat_i

wb_dat_i in std_logic_vector ( 7 downto 0 )

Port

wb_rst_i

wb_rst_i in std_logic

Port

wb_wacc

wb_wacc in std_logic

Port

---

The documentation for this class was generated from the following file:

• components/opencores_i2c/firmware/hdl/i2c_master_registers.vhd