rtl Architecture Reference

Processes
retime	( ipb_clk )
retime_resets	( drp_clk , xcvr_ctrl_reg )

Signals
xcvr_status	ipb_reg_v ( 3 downto 0 )
xcvr_ctrl_reg	ipb_reg_v ( 1 downto 0 )
softrsttx	std_logic
softrstrx	std_logic
gttxreset	std_logic
gtrxreset	std_logic
loopback	std_logic_vector ( 2 downto 0 )
tx_prbs	std_logic_vector ( 2 downto 0 )
tx_reset_done_bits	std_logic_vector ( 7 downto 0 )
rx_reset_done_bits	std_logic_vector ( 7 downto 0 )
rx_byteisaligned_bits	std_logic_vector ( 7 downto 0 )
q1_ref_lost	std_logic
q0_ref_lost	std_logic
q1_lock_out	std_logic
q0_lock_out	std_logic

Instantiations
xcvr_control	ipbus_ctrlreg_v <Entity ipbus_ctrlreg_v>

Member Function Documentation

retime()

retime

(

ipb_clk

)

retime_resets()

retime_resets (   drp_clk ,   xcvr_ctrl_reg   )

Process

Member Data Documentation

gtrxreset

gtrxreset std_logic

Signal

gttxreset

gttxreset std_logic

Signal

loopback

loopback std_logic_vector ( 2 downto 0 )

Signal

q0_lock_out

q0_lock_out std_logic

Signal

q0_ref_lost

q0_ref_lost std_logic

Signal

q1_lock_out

q1_lock_out std_logic

Signal

q1_ref_lost

q1_ref_lost std_logic

Signal

rx_byteisaligned_bits

rx_byteisaligned_bits std_logic_vector ( 7 downto 0 )

Signal

rx_reset_done_bits

rx_reset_done_bits std_logic_vector ( 7 downto 0 )

Signal

softrstrx

softrstrx std_logic

Signal

softrsttx

softrsttx std_logic

Signal

tx_prbs

tx_prbs std_logic_vector ( 2 downto 0 )

Signal

tx_reset_done_bits

tx_reset_done_bits std_logic_vector ( 7 downto 0 )

Signal

xcvr_control

xcvr_control ipbus_ctrlreg_v

Instantiation

xcvr_ctrl_reg

xcvr_ctrl_reg ipb_reg_v ( 1 downto 0 )

Signal

xcvr_status

xcvr_status ipb_reg_v ( 3 downto 0 )

Signal

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The documentation for this class was generated from the following file:

• FTM/Control/hdl/ipbus_con_2quad_control.vhd