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My Project
v0.0.16
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Processes | |
| PROCESS_272 | ( clk ) |
| PROCESS_832 | ( clk ) |
Signals | |
| w_ctr | unsigned ( 15 downto 0 ) |
| r_ctr | unsigned ( 15 downto 0 ) |
| ack | std_logic |
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Process |
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Process |
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Signal |
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Signal |
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Signal |
1.8.13