My Project  v0.0.16
Signals | Processes
rtl Architecture Reference

Processes

PROCESS_272  ( clk )
PROCESS_832  ( clk )

Signals

w_ctr  unsigned ( 15 downto 0 )
r_ctr  unsigned ( 15 downto 0 )
ack  std_logic

Member Function Documentation

◆ PROCESS_272()

PROCESS_272 (   clk  
)
Process

◆ PROCESS_832()

PROCESS_832 (   clk  
)
Process

Member Data Documentation

◆ ack

ack std_logic
Signal

◆ r_ctr

r_ctr unsigned ( 15 downto 0 )
Signal

◆ w_ctr

w_ctr unsigned ( 15 downto 0 )
Signal

The documentation for this class was generated from the following file: