ipbus_ctrl Entity Reference

Inheritance diagram for ipbus_ctrl:

Collaboration diagram for ipbus_ctrl:

Entities
rtl	architecture

Libraries
ieee

Use Clauses
std_logic_1164
ipbus	Package <ipbus>
ipbus_trans_decl	Package <ipbus_trans_decl>

Generics
MAC_CFG	ipb_mac_cfg := EXTERNAL
IP_CFG	ipb_ip_cfg := EXTERNAL
BUFWIDTH	natural := 4
INTERNALWIDTH	natural := 1
ADDRWIDTH	natural := 11
SECONDARYPORT	std_logic := ' 0 '
N_OOB	natural := 0
IPBUSPORT	std_logic_vector ( 15 DOWNTO 0 ) := x " C351 "

Ports
mac_clk	in std_logic
rst_macclk	in std_logic
ipb_clk	in std_logic
rst_ipb	in std_logic
mac_rx_data	in std_logic_vector ( 7 downto 0 )
mac_rx_valid	in std_logic
mac_rx_last	in std_logic
mac_rx_error	in std_logic
mac_tx_data	out std_logic_vector ( 7 downto 0 )
mac_tx_valid	out std_logic
mac_tx_last	out std_logic
mac_tx_error	out std_logic
mac_tx_ready	in std_logic
ipb_out	out ipb_wbus
ipb_in	in ipb_rbus
ipb_req	out std_logic
ipb_grant	in std_logic := ' 1 '
mac_addr	in std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
ip_addr	in std_logic_vector ( 31 downto 0 ) := X " 00000000 "
ipbus_port	in std_logic_vector ( 15 downto 0 ) := x " C351 "
enable	in std_logic := ' 1 '
RARP_select	in std_logic := ' 0 '
actual_mac_addr	out std_logic_vector ( 47 downto 0 )
actual_ip_addr	out std_logic_vector ( 31 downto 0 )
Got_IP_addr	out std_logic
pkt	out std_logic
pkt_oob	out std_logic
oob_in	in ipbus_trans_in_array ( N_OOB - 1 downto 0 ) := ( others = > ( ' 0 ' , X " 00000000 " , ' 0 ' ) )
oob_out	out ipbus_trans_out_array ( N_OOB - 1 downto 0 )

Member Data Documentation

actual_ip_addr

actual_ip_addr out std_logic_vector ( 31 downto 0 )

Port

actual_mac_addr

actual_mac_addr out std_logic_vector ( 47 downto 0 )

Port

ADDRWIDTH

ADDRWIDTH natural := 11

Generic

BUFWIDTH

BUFWIDTH natural := 4

Generic

enable

enable in std_logic := ' 1 '

Port

Got_IP_addr

Got_IP_addr out std_logic

Port

ieee

ieee

Library

INTERNALWIDTH

INTERNALWIDTH natural := 1

Generic

ip_addr

ip_addr in std_logic_vector ( 31 downto 0 ) := X " 00000000 "

Port

IP_CFG

IP_CFG ipb_ip_cfg := EXTERNAL

Generic

ipb_clk

ipb_clk in std_logic

Port

ipb_grant

ipb_grant in std_logic := ' 1 '

Port

ipb_in

ipb_in in ipb_rbus

Port

ipb_out

ipb_out out ipb_wbus

Port

ipb_req

ipb_req out std_logic

Port

ipbus

ipbus

Package

ipbus_port

ipbus_port in std_logic_vector ( 15 downto 0 ) := x " C351 "

Port

ipbus_trans_decl

ipbus_trans_decl

Package

IPBUSPORT

IPBUSPORT std_logic_vector ( 15 DOWNTO 0 ) := x " C351 "

Generic

mac_addr

mac_addr in std_logic_vector ( 47 downto 0 ) := X " 000000000000 "

Port

MAC_CFG

MAC_CFG ipb_mac_cfg := EXTERNAL

Generic

mac_clk

mac_clk in std_logic

Port

mac_rx_data

mac_rx_data in std_logic_vector ( 7 downto 0 )

Port

mac_rx_error

mac_rx_error in std_logic

Port

mac_rx_last

mac_rx_last in std_logic

Port

mac_rx_valid

mac_rx_valid in std_logic

Port

mac_tx_data

mac_tx_data out std_logic_vector ( 7 downto 0 )

Port

mac_tx_error

mac_tx_error out std_logic

Port

mac_tx_last

mac_tx_last out std_logic

Port

mac_tx_ready

mac_tx_ready in std_logic

Port

mac_tx_valid

mac_tx_valid out std_logic

Port

N_OOB

N_OOB natural := 0

Generic

oob_in

oob_in in ipbus_trans_in_array ( N_OOB - 1 downto 0 ) := ( others = > ( ' 0 ' , X " 00000000 " , ' 0 ' ) )

Port

oob_out

oob_out out ipbus_trans_out_array ( N_OOB - 1 downto 0 )

Port

pkt

pkt out std_logic

Port

pkt_oob

pkt_oob out std_logic

Port

RARP_select

RARP_select in std_logic := ' 0 '

Port

rst_ipb

rst_ipb in std_logic

Port

rst_macclk

rst_macclk in std_logic

Port

SECONDARYPORT

SECONDARYPORT std_logic := ' 0 '

Generic

std_logic_1164

std_logic_1164

Package

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd