rtl Architecture Reference

Processes
PROCESS_273	( clk )
PROCESS_274	( clk )
PROCESS_833	( clk )
PROCESS_834	( clk )

Constants
ADDR_WIDTH	integer := integer_max ( calc_width ( N_CTRL ) , calc_width ( N_STAT ) )

Signals
sel	integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
reg	ipb_reg_v ( N_CTRL - 1 downto 0 )
si	ipb_reg_v ( 2 ** ADDR_WIDTH - 1 downto 0 )
ri	ipb_reg_v ( 2 ** ADDR_WIDTH - 1 downto 0 )
stat_cyc	std_logic
cw_cyc	std_logic

Member Function Documentation

PROCESS_273()

PROCESS_273 (   clk   )

Process

PROCESS_274()

PROCESS_274 (   clk   )

Process

PROCESS_833()

PROCESS_833 (   clk   )

Process

PROCESS_834()

PROCESS_834 (   clk   )

Process

Member Data Documentation

ADDR_WIDTH

ADDR_WIDTH integer := integer_max ( calc_width ( N_CTRL ) , calc_width ( N_STAT ) )

Constant

cw_cyc

cw_cyc std_logic

Signal

reg

reg ipb_reg_v ( N_CTRL - 1 downto 0 )

Signal

ri

ri ipb_reg_v ( 2 ** ADDR_WIDTH - 1 downto 0 )

Signal

sel

sel integer range 0 to 2 ** ADDR_WIDTH - 1 := 0

Signal

si

si ipb_reg_v ( 2 ** ADDR_WIDTH - 1 downto 0 )

Signal

stat_cyc

stat_cyc std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd