rtl Architecture Reference

Processes
memory_check	( data_clk , ram_index , end_of_ram )

Constants
RAM_SIZE	natural := 2 ** ( DPRAM_ADDR_WIDTH - 1 )
COMPLETE_FRAMES	natural := ( RAM_SIZE / FRAME_SIZE )
LAST_MEMORY	natural := ( COMPLETE_FRAMES * FRAME_SIZE ) - 1
LAST_MEMORY_U	unsigned ( DPRAM_ADDR_WIDTH - 2 downto 0 ) := to_unsigned ( LAST_MEMORY , DPRAM_ADDR_WIDTH - 1 )

Signals
pointer_addr	std_logic_vector ( DPRAM_ADDR_WIDTH - 2 downto 0 )
ram_index	unsigned ( DPRAM_ADDR_WIDTH - 2 downto 0 )
ipbw	ipb_wbus_array ( 1 downto 0 )
ipbr	ipb_rbus_array ( 1 downto 0 )
null_data	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
null_ctrl	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
web	std_logic
eof	std_logic
end_of_ram	std_logic := ' 0 '
use_ram	std_logic := ' 0 '
source_data	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
source_ctrl	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
ram_data	mgt_data
dummy_data	mgt_data

Instantiations
framer	framing_sync_logic <Entity framing_sync_logic>
ram_pointer	tx_ram_pointer <Entity tx_ram_pointer>
block_decode	ipbus_fabric_merge <Entity ipbus_fabric_merge>
dssram	ipbus_dpram_frame_init <Entity ipbus_dpram_frame_init>
ctrlram	ipbus_dpram_ctrl_init <Entity ipbus_dpram_ctrl_init>
dummy	dummy_frame_generator <Entity dummy_frame_generator>

Member Function Documentation

memory_check()

memory_check	(		data_clk,
			ram_index,
			end_of_ram
	)

Member Data Documentation

block_decode

block_decode ipbus_fabric_merge

Instantiation

COMPLETE_FRAMES

COMPLETE_FRAMES natural := ( RAM_SIZE / FRAME_SIZE )

Constant

ctrlram

ctrlram ipbus_dpram_ctrl_init

Instantiation

dssram

dssram ipbus_dpram_frame_init

Instantiation

dummy

dummy dummy_frame_generator

Instantiation

dummy_data

dummy_data mgt_data

Signal

end_of_ram

end_of_ram std_logic := ' 0 '

Signal

eof

eof std_logic

Signal

framer

framer framing_sync_logic

Instantiation

ipbr

ipbr ipb_rbus_array ( 1 downto 0 )

Signal

ipbw

ipbw ipb_wbus_array ( 1 downto 0 )

Signal

LAST_MEMORY

LAST_MEMORY natural := ( COMPLETE_FRAMES * FRAME_SIZE ) - 1

Constant

LAST_MEMORY_U

LAST_MEMORY_U unsigned ( DPRAM_ADDR_WIDTH - 2 downto 0 ) := to_unsigned ( LAST_MEMORY , DPRAM_ADDR_WIDTH - 1 )

Constant

null_ctrl

null_ctrl std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Signal

null_data

null_data std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

pointer_addr

pointer_addr std_logic_vector ( DPRAM_ADDR_WIDTH - 2 downto 0 )

Signal

ram_data

ram_data mgt_data

Signal

ram_index

ram_index unsigned ( DPRAM_ADDR_WIDTH - 2 downto 0 )

Signal

ram_pointer

ram_pointer tx_ram_pointer

Instantiation

RAM_SIZE

RAM_SIZE natural := 2 ** ( DPRAM_ADDR_WIDTH - 1 )

Constant

source_ctrl

source_ctrl std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Signal

source_data

source_data std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

use_ram

use_ram std_logic := ' 0 '

Signal

web

web std_logic

Signal

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The documentation for this class was generated from the following file:

• common/DSS_buffer/hdl/ipbus_data_source.vhd