rtl Architecture Reference

Processes
PROCESS_277	( clk )
PROCESS_278	( rclk )
PROCESS_837	( clk )
PROCESS_838	( rclk )

Types
ram_array	( 2 ** ADDR_WIDTH - 1 downto 0 ) std_logic_vector ( 17 downto 0 )

Signals
sel	integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
rsel	integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
ack	std_logic

Shared Variables
ram_bh	shared ram_array
ram_th	shared ram_array

Member Function Documentation

PROCESS_277()

PROCESS_277 (   clk   )

Process

PROCESS_278()

PROCESS_278 (   rclk   )

Process

PROCESS_837()

PROCESS_837 (   clk   )

Process

PROCESS_838()

PROCESS_838 (   rclk   )

Process

Member Data Documentation

ack

ack std_logic

Signal

ram_array

ram_array ( 2 ** ADDR_WIDTH - 1 downto 0 ) std_logic_vector ( 17 downto 0 )

Type

ram_bh

ram_bh shared ram_array

Shared Variable

ram_th

ram_th shared ram_array

Shared Variable

rsel

rsel integer range 0 to 2 ** ADDR_WIDTH - 1 := 0

Signal

sel

sel integer range 0 to 2 ** ADDR_WIDTH - 1 := 0

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_slaves/firmware/hdl/ipbus_dpram36.vhd