My Project
v0.0.16
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Processes | |
PROCESS_275 | ( clk ) |
PROCESS_276 | ( rclk ) |
PROCESS_835 | ( clk ) |
PROCESS_836 | ( rclk ) |
Types | |
ram_array | ( 2 ** ADDR_WIDTH - 1 downto 0 ) std_logic_vector ( 31 downto 0 ) |
Signals | |
sel | integer range 0 to 2 ** ADDR_WIDTH - 1 := 0 |
rsel | integer range 0 to 2 ** ADDR_WIDTH - 1 := 0 |
ack | std_logic |
Shared Variables | |
ram | shared ram_array |
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Process |
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Process |
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Process |
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Process |
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Signal |
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Type |
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Signal |
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Signal |