My Project  v0.0.16
Types | Shared Variables | Signals | Processes
rtl Architecture Reference

Processes

PROCESS_275  ( clk )
PROCESS_276  ( rclk )
PROCESS_835  ( clk )
PROCESS_836  ( rclk )

Types

ram_array ( 2 ** ADDR_WIDTH - 1 downto 0 ) std_logic_vector ( 31 downto 0 )

Signals

sel  integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
rsel  integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
ack  std_logic

Shared Variables

ram  shared ram_array

Member Function Documentation

◆ PROCESS_275()

PROCESS_275 (   clk  
)
Process

◆ PROCESS_276()

PROCESS_276 (   rclk  
)
Process

◆ PROCESS_835()

PROCESS_835 (   clk  
)
Process

◆ PROCESS_836()

PROCESS_836 (   rclk  
)
Process

Member Data Documentation

◆ ack

ack std_logic
Signal

◆ ram

ram shared ram_array
Shared Variable

◆ ram_array

ram_array ( 2 ** ADDR_WIDTH - 1 downto 0 ) std_logic_vector ( 31 downto 0 )
Type

◆ rsel

rsel integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
Signal

◆ sel

sel integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
Signal

The documentation for this class was generated from the following file: