rtl Architecture Reference

Processes
PROCESS_2	( clk )
PROCESS_3	( rclk )

Types
ram_array	( 0 to 2 ** ADDR_WIDTH - 1 ) std_logic_vector ( 3 downto 0 )

Signals
sel	integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
rsel	integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
ack	std_logic
rdata	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
wdata	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Shared Variables
ram	shared ram_array := := ( " 0001 " , " 0000 " , " 0000 " , " 0000 " , " 0000 " , " 0000 " , " 0000 " , others = > " 0000 " )

Member Function Documentation

PROCESS_2()

PROCESS_2 (   clk   )

Process

PROCESS_3()

PROCESS_3 (   rclk   )

Process

Member Data Documentation

ack

ack std_logic

Signal

ram

ram shared ram_array := := ( " 0001 " , " 0000 " , " 0000 " , " 0000 " , " 0000 " , " 0000 " , " 0000 " , others = > " 0000 " )

Shared Variable

ram_array

ram_array ( 0 to 2 ** ADDR_WIDTH - 1 ) std_logic_vector ( 3 downto 0 )

Type

rdata

rdata std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Signal

rsel

rsel integer range 0 to 2 ** ADDR_WIDTH - 1 := 0

Signal

sel

sel integer range 0 to 2 ** ADDR_WIDTH - 1 := 0

Signal

wdata

wdata std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Signal

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The documentation for this class was generated from the following file:

• common/DSS_buffer/hdl/ipbus_dpram_ctrl_init.vhd