rtl Architecture Reference

Processes
PROCESS_4	( clk )
PROCESS_5	( rclk )

Types
ram_array	( 0 to 2 ** ADDR_WIDTH - 1 ) std_logic_vector ( 31 downto 0 )

Signals
sel	integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
rsel	integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
ack	std_logic

Shared Variables
ram	shared ram_array := := ( X " 000000BC " , X " 00000001 " , X " 00000002 " , X " 00000003 " , X " 00000004 " , X " 00000005 " , X " 00000006 " , X " 00000007 " , others = > X " 00000000 " )

Member Function Documentation

PROCESS_4()

PROCESS_4 (   clk   )

Process

PROCESS_5()

PROCESS_5 (   rclk   )

Process

Member Data Documentation

ack

ack std_logic

Signal

ram

ram shared ram_array := := ( X " 000000BC " , X " 00000001 " , X " 00000002 " , X " 00000003 " , X " 00000004 " , X " 00000005 " , X " 00000006 " , X " 00000007 " , others = > X " 00000000 " )

Shared Variable

ram_array

ram_array ( 0 to 2 ** ADDR_WIDTH - 1 ) std_logic_vector ( 31 downto 0 )

Type

rsel

rsel integer range 0 to 2 ** ADDR_WIDTH - 1 := 0

Signal

sel

sel integer range 0 to 2 ** ADDR_WIDTH - 1 := 0

Signal

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The documentation for this class was generated from the following file:

• common/DSS_buffer/hdl/ipbus_dpram_frame_init.vhd