My Project
v0.0.16
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Processes | |
PROCESS_280 | ( clk ) |
PROCESS_840 | ( clk ) |
Signals | |
emac1sel | std_logic |
mdiocyc | std_logic |
acyc | std_logic |
dcyc | std_logic |
dcyc_d | std_logic |
addr | std_logic_vector ( 9 downto 0 ) |
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Process |
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Process |
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Signal |
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Signal |
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Signal |
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Signal |
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Signal |
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Signal |