|
My Project
v0.0.16
|
Processes | |
| PROCESS_280 | ( clk ) |
| PROCESS_840 | ( clk ) |
Signals | |
| emac1sel | std_logic |
| mdiocyc | std_logic |
| acyc | std_logic |
| dcyc | std_logic |
| dcyc_d | std_logic |
| addr | std_logic_vector ( 9 downto 0 ) |
|
Process |
|
Process |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
1.8.13