My Project  v0.0.16
Signals | Processes
rtl Architecture Reference

Processes

PROCESS_280  ( clk )
PROCESS_840  ( clk )

Signals

emac1sel  std_logic
mdiocyc  std_logic
acyc  std_logic
dcyc  std_logic
dcyc_d  std_logic
addr  std_logic_vector ( 9 downto 0 )

Member Function Documentation

◆ PROCESS_280()

PROCESS_280 (   clk  
)
Process

◆ PROCESS_840()

PROCESS_840 (   clk  
)
Process

Member Data Documentation

◆ acyc

acyc std_logic
Signal

◆ addr

addr std_logic_vector ( 9 downto 0 )
Signal

◆ dcyc

dcyc std_logic
Signal

◆ dcyc_d

dcyc_d std_logic
Signal

◆ emac1sel

emac1sel std_logic
Signal

◆ mdiocyc

mdiocyc std_logic
Signal

The documentation for this class was generated from the following file: