My Project  v0.0.16
Signals | Instantiations
rtl Architecture Reference

Signals

ipbw  ipb_wbus_array ( N_SLAVES - 1 downto 0 )
ipbr  ipb_rbus_array ( N_SLAVES - 1 downto 0 )
ctrl  ipb_reg_v ( 0 downto 0 )
stat  ipb_reg_v ( 0 downto 0 )

Instantiations

fabric  ipbus_fabric_sel <Entity ipbus_fabric_sel>
slave0  ipbus_ctrlreg_v <Entity ipbus_ctrlreg_v>
slave1  ipbus_reg_v <Entity ipbus_reg_v>
slave4  ipbus_ram <Entity ipbus_ram>
slave5  ipbus_peephole_ram <Entity ipbus_peephole_ram>
fabric  ipbus_fabric_sel <Entity ipbus_fabric_sel>
slave0  ipbus_ctrlreg_v <Entity ipbus_ctrlreg_v>
slave1  ipbus_reg_v <Entity ipbus_reg_v>
slave4  ipbus_ram <Entity ipbus_ram>
slave5  ipbus_peephole_ram <Entity ipbus_peephole_ram>

Member Data Documentation

◆ ctrl

ctrl ipb_reg_v ( 0 downto 0 )
Signal

◆ fabric [1/2]

fabric ipbus_fabric_sel
Instantiation

◆ fabric [2/2]

fabric ipbus_fabric_sel
Instantiation

◆ ipbr

ipbr ipb_rbus_array ( N_SLAVES - 1 downto 0 )
Signal

◆ ipbw

ipbw ipb_wbus_array ( N_SLAVES - 1 downto 0 )
Signal

◆ slave0 [1/2]

slave0 ipbus_ctrlreg_v
Instantiation

◆ slave0 [2/2]

slave0 ipbus_ctrlreg_v
Instantiation

◆ slave1 [1/2]

slave1 ipbus_reg_v
Instantiation

◆ slave1 [2/2]

slave1 ipbus_reg_v
Instantiation

◆ slave4 [1/2]

slave4 ipbus_ram
Instantiation

◆ slave4 [2/2]

slave4 ipbus_ram
Instantiation

◆ slave5 [1/2]

slave5 ipbus_peephole_ram
Instantiation

◆ slave5 [2/2]

slave5 ipbus_peephole_ram
Instantiation

◆ stat

stat ipb_reg_v ( 0 downto 0 )
Signal

The documentation for this class was generated from the following file: