My Project  v0.0.16
Constants | Signals | Types | Attributes | Processes
rtl Architecture Reference

Processes

PROCESS_281  ( clk )
PROCESS_282  ( clkin (i ) )
PROCESS_841  ( clk )
PROCESS_842  ( clkin (i ) )

Constants

n_clk  natural := 2 ** ADDR_WIDTH

Types

ctr_array ( n_clk - 1 downto 0 ) unsigned ( 23 downto 0 )

Signals

ctr_s  unsigned ( 15 downto 0 ) := X " 0000 "
ctr  ctr_array := ( others = > X " 000000 " )
samp  ctr_array
samp_i  ctr_array
go  std_logic
go_s  std_logic_vector ( n_clk - 1 downto 0 )
go_s2  std_logic_vector ( n_clk - 1 downto 0 )
go_s3  std_logic_vector ( n_clk - 1 downto 0 )
sel  integer range 0 to 2 ** ADDR_WIDTH := 0

Attributes

KEEP  string
KEEP  go_s : signal is " TRUE "

Member Function Documentation

◆ PROCESS_281()

PROCESS_281 (   clk  
)
Process

◆ PROCESS_282()

PROCESS_282 (   clkin (i )  
)
Process

◆ PROCESS_841()

PROCESS_841 (   clk  
)
Process

◆ PROCESS_842()

PROCESS_842 (   clkin (i )  
)
Process

Member Data Documentation

◆ ctr

ctr ctr_array := ( others = > X " 000000 " )
Signal

◆ ctr_array

ctr_array ( n_clk - 1 downto 0 ) unsigned ( 23 downto 0 )
Type

◆ ctr_s

ctr_s unsigned ( 15 downto 0 ) := X " 0000 "
Signal

◆ go

go std_logic
Signal

◆ go_s

go_s std_logic_vector ( n_clk - 1 downto 0 )
Signal

◆ go_s2

go_s2 std_logic_vector ( n_clk - 1 downto 0 )
Signal

◆ go_s3

go_s3 std_logic_vector ( n_clk - 1 downto 0 )
Signal

◆ KEEP [1/2]

KEEP string
Attribute

◆ KEEP [2/2]

KEEP go_s : signal is " TRUE "
Attribute

◆ n_clk

n_clk natural := 2 ** ADDR_WIDTH
Constant

◆ samp

samp ctr_array
Signal

◆ samp_i

samp_i ctr_array
Signal

◆ sel

sel integer range 0 to 2 ** ADDR_WIDTH := 0
Signal

The documentation for this class was generated from the following file: