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My Project
v0.0.16
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Processes | |
| PROCESS_281 | ( clk ) |
| PROCESS_282 | ( clkin (i ) ) |
| PROCESS_841 | ( clk ) |
| PROCESS_842 | ( clkin (i ) ) |
Constants | |
| n_clk | natural := 2 ** ADDR_WIDTH |
Types | |
| ctr_array | ( n_clk - 1 downto 0 ) unsigned ( 23 downto 0 ) |
Signals | |
| ctr_s | unsigned ( 15 downto 0 ) := X " 0000 " |
| ctr | ctr_array := ( others = > X " 000000 " ) |
| samp | ctr_array |
| samp_i | ctr_array |
| go | std_logic |
| go_s | std_logic_vector ( n_clk - 1 downto 0 ) |
| go_s2 | std_logic_vector ( n_clk - 1 downto 0 ) |
| go_s3 | std_logic_vector ( n_clk - 1 downto 0 ) |
| sel | integer range 0 to 2 ** ADDR_WIDTH := 0 |
Attributes | |
| KEEP | string |
| KEEP | go_s : signal is " TRUE " |
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Process |
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Process |
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Process |
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Process |
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Signal |
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Signal |
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Attribute |
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Constant |
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Signal |
1.8.13