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ipbus_ftm_fpga_id_version Entity Reference
Inheritance diagram for ipbus_ftm_fpga_id_version:
Inheritance graph
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Entities

rtl  architecture
 

Libraries

IEEE 
unisim 

Use Clauses

STD_LOGIC_1164 
numeric_std 
ipbus  Package <ipbus>
VComponents 

Generics

XML_VERSION  std_logic_vector ( 31 downto 0 ) := x " 00000000 "
XML_HASH  std_logic_vector ( 31 downto 0 ) := x " 00000000 "
GLOBAL_FWVERSION  std_logic_vector ( 31 downto 0 ) := x " 00000000 "
GLOBAL_FWHASH  std_logic_vector ( 31 downto 0 ) := x " 00000000 "
GLOBAL_FWDATE  std_logic_vector ( 31 downto 0 ) := x " 00000000 "
GLOBAL_FWTIME  std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Ports

ipbus_in   in ipb_wbus
ipbus_out   out ipb_rbus
Module_ID   in std_logic_vector ( 31 downto 0 )

Member Data Documentation

◆ GLOBAL_FWDATE

GLOBAL_FWDATE std_logic_vector ( 31 downto 0 ) := x " 00000000 "
Generic

◆ GLOBAL_FWHASH

GLOBAL_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "
Generic

◆ GLOBAL_FWTIME

GLOBAL_FWTIME std_logic_vector ( 31 downto 0 ) := x " 00000000 "
Generic

◆ GLOBAL_FWVERSION

GLOBAL_FWVERSION std_logic_vector ( 31 downto 0 ) := x " 00000000 "
Generic

◆ IEEE

IEEE
Library

◆ ipbus

ipbus
Package

◆ ipbus_in

ipbus_in in ipb_wbus
Port

◆ ipbus_out

ipbus_out out ipb_rbus
Port

◆ Module_ID

Module_ID in std_logic_vector ( 31 downto 0 )
Port

◆ numeric_std

numeric_std
Package

◆ STD_LOGIC_1164

STD_LOGIC_1164
Package

◆ unisim

unisim
Library

◆ VComponents

VComponents
Package

◆ XML_HASH

XML_HASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "
Generic

◆ XML_VERSION

XML_VERSION std_logic_vector ( 31 downto 0 ) := x " 00000000 "
Generic

The documentation for this class was generated from the following file: