struct Architecture Reference

Processes
PROCESS_393	( ipb_clk , addr , ipb_in .ipb_wdata , ipb_in .ipb_strobe , ipb_in .ipb_write , ack )
PROCESS_394	( clock , write_pulse0 )
PROCESS_395	( clock , use_ttcfmc , ttc_bcrst )
PROCESS_396	( clock , Orbit_BC_counter )
PROCESS_397	( clock , Orbit_BC_counter )

Constants
START_N	natural := 1
DEFAULT_PERIOD	std_logic_vector ( 11 downto 0 ) := std_logic_vector ( to_unsigned ( N_BCS_ORBIT , 12 ) )
DEFAULT_DELAY	natural := 3

Signals
ack	std_logic := ' 0 '
addr	natural range 0 to 3
write_pulse0	std_logic := ' 0 '
write_pulse0_sync	std_logic := ' 0 '
run_com	std_logic := ' 0 '
local_bcrst	std_logic := ' 0 '
use_ttcfmc	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
use_ttcfmc_r	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
ttc_bcrst_r	std_logic := ' 0 '
ttc_l1a_r	std_logic := ' 0 '
ttc_ecr_r	std_logic := ' 0 '
ftm_bcrst	std_logic := ' 0 '
orbit_creg	std_logic_vector ( 11 downto 0 ) := DEFAULT_PERIOD
orbit_size	natural range 0 to N_BCS_ORBIT
onboard_delay	std_logic_vector ( 4 downto 0 ) := std_logic_vector ( to_unsigned ( DEFAULT_DELAY , 5 ) )
Orbit_BC_counter	natural range 0 to N_BCS_ORBIT := START_N

Attributes
mark_debug	string
mark_debug	local_bcrst : signal is " true "
mark_debug	ttc_bcrst_r : signal is " true "
mark_debug	ttc_l1a_r : signal is " true "
mark_debug	ttc_ecr_r : signal is " true "

Instantiations
delaycomp	srlc32e

Member Function Documentation

PROCESS_393()

PROCESS_393 (   ipb_clk ,   addr ,   ipb_in .ipb_wdata ,   ipb_in .ipb_strobe ,   ipb_in .ipb_write ,   ack   )

Process

PROCESS_394()

PROCESS_394 (   clock ,   write_pulse0   )

Process

PROCESS_395()

PROCESS_395 (   clock ,   use_ttcfmc ,   ttc_bcrst   )

Process

PROCESS_396()

PROCESS_396 (   clock ,   Orbit_BC_counter   )

Process

PROCESS_397()

PROCESS_397 (   clock ,   Orbit_BC_counter   )

Process

Member Data Documentation

ack

ack std_logic := ' 0 '

Signal

addr

addr natural range 0 to 3

Signal

DEFAULT_DELAY

DEFAULT_DELAY natural := 3

Constant

DEFAULT_PERIOD

DEFAULT_PERIOD std_logic_vector ( 11 downto 0 ) := std_logic_vector ( to_unsigned ( N_BCS_ORBIT , 12 ) )

Constant

delaycomp

delaycomp srlc32e

Instantiation

ftm_bcrst

ftm_bcrst std_logic := ' 0 '

Signal

local_bcrst

local_bcrst std_logic := ' 0 '

Signal

mark_debug [1/5]

mark_debug string

Attribute

mark_debug [2/5]

mark_debug local_bcrst : signal is " true "

Attribute

mark_debug [3/5]

mark_debug ttc_bcrst_r : signal is " true "

Attribute

mark_debug [4/5]

mark_debug ttc_l1a_r : signal is " true "

Attribute

mark_debug [5/5]

mark_debug ttc_ecr_r : signal is " true "

Attribute

onboard_delay

onboard_delay std_logic_vector ( 4 downto 0 ) := std_logic_vector ( to_unsigned ( DEFAULT_DELAY , 5 ) )

Signal

Orbit_BC_counter

Orbit_BC_counter natural range 0 to N_BCS_ORBIT := START_N

Signal

orbit_creg

orbit_creg std_logic_vector ( 11 downto 0 ) := DEFAULT_PERIOD

Signal

orbit_size

orbit_size natural range 0 to N_BCS_ORBIT

Signal

run_com

run_com std_logic := ' 0 '

Signal

START_N

START_N natural := 1

Constant

ttc_bcrst_r

ttc_bcrst_r std_logic := ' 0 '

Signal

ttc_ecr_r

ttc_ecr_r std_logic := ' 0 '

Signal

ttc_l1a_r

ttc_l1a_r std_logic := ' 0 '

Signal

use_ttcfmc

use_ttcfmc std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )

Signal

use_ttcfmc_r

use_ttcfmc_r std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )

Signal

write_pulse0

write_pulse0 std_logic := ' 0 '

Signal

write_pulse0_sync

write_pulse0_sync std_logic := ' 0 '

Signal

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The documentation for this class was generated from the following file:

• FTM/Control/hdl/ipbus_module_playback.vhd