rtl Architecture Reference

Processes
PROCESS_283	( clk )
PROCESS_843	( clk )

Components
dpram_32x10b_32x10b

Signals
d_req	std_logic_vector ( 31 downto 0 )
d_resp	std_logic_vector ( 31 downto 0 )
ram_d	std_logic_vector ( 31 downto 0 )
we_req	std_logic_vector ( 0 downto 0 )
we_resp	std_logic_vector ( 0 downto 0 )
web_resp	std_logic_vector ( 0 downto 0 )
reg_en	std_logic
ack	std_logic

Instantiations
req_ram	dpram_32x10b_32x10b
resp_ram	dpram_32x10b_32x10b
req_ram	dpram_32x10b_32x10b
resp_ram	dpram_32x10b_32x10b

Member Function Documentation

PROCESS_283()

PROCESS_283 (   clk   )

Process

PROCESS_843()

PROCESS_843 (   clk   )

Process

Member Data Documentation

ack

ack std_logic

Signal

d_req

d_req std_logic_vector ( 31 downto 0 )

Signal

d_resp

d_resp std_logic_vector ( 31 downto 0 )

Signal

dpram_32x10b_32x10b

dpram_32x10b_32x10b

Component

ram_d

ram_d std_logic_vector ( 31 downto 0 )

Signal

reg_en

reg_en std_logic

Signal

req_ram [1/2]

req_ram dpram_32x10b_32x10b

Instantiation

req_ram [2/2]

req_ram dpram_32x10b_32x10b

Instantiation

resp_ram [1/2]

resp_ram dpram_32x10b_32x10b

Instantiation

resp_ram [2/2]

resp_ram dpram_32x10b_32x10b

Instantiation

we_req

we_req std_logic_vector ( 0 downto 0 )

Signal

we_resp

we_resp std_logic_vector ( 0 downto 0 )

Signal

web_resp

web_resp std_logic_vector ( 0 downto 0 )

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_slaves/firmware/hdl/ipbus_oob_test.vhd