rtl Architecture Reference

Processes
PROCESS_284	( clk )
PROCESS_844	( clk )

Types
reg_array	( 2 ** ADDR_WIDTH - 1 downto 0 ) std_logic_vector ( 31 downto 0 )

Signals
reg	reg_array
sel	integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
ptr	unsigned ( ADDR_WIDTH - 1 downto 0 )
data	std_logic_vector ( 31 downto 0 )

Member Function Documentation

PROCESS_284()

PROCESS_284 (   clk   )

Process

PROCESS_844()

PROCESS_844 (   clk   )

Process

Member Data Documentation

data

data std_logic_vector ( 31 downto 0 )

Signal

ptr

ptr unsigned ( ADDR_WIDTH - 1 downto 0 )

Signal

reg

reg reg_array

Signal

reg_array

reg_array ( 2 ** ADDR_WIDTH - 1 downto 0 ) std_logic_vector ( 31 downto 0 )

Type

sel

sel integer range 0 to 2 ** ADDR_WIDTH - 1 := 0

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_slaves/firmware/hdl/ipbus_peephole_ram.vhd