rtl Architecture Reference

Processes
PROCESS_294	( clk )
PROCESS_295	( wclk )
PROCESS_854	( clk )
PROCESS_855	( wclk )

Types
ram_array	( 2 ** ADDR_WIDTH - 1 downto 0 ) std_logic_vector ( 71 downto 0 )

Signals
sel	integer range 0 to 2 ** ADDR_WIDTH - 3 := 0
rsel	integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
rdata	std_logic_vector ( 17 downto 0 )
ack	std_logic

Shared Variables
ram	shared ram_array

Member Function Documentation

PROCESS_294()

PROCESS_294 (   clk   )

Process

PROCESS_295()

PROCESS_295 (   wclk   )

Process

PROCESS_854()

PROCESS_854 (   clk   )

Process

PROCESS_855()

PROCESS_855 (   wclk   )

Process

Member Data Documentation

ack

ack std_logic

Signal

ram

ram shared ram_array

Shared Variable

ram_array

ram_array ( 2 ** ADDR_WIDTH - 1 downto 0 ) std_logic_vector ( 71 downto 0 )

Type

rdata

rdata std_logic_vector ( 17 downto 0 )

Signal

rsel

rsel integer range 0 to 2 ** ADDR_WIDTH - 1 := 0

Signal

sel

sel integer range 0 to 2 ** ADDR_WIDTH - 3 := 0

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_slaves/firmware/hdl/ipbus_sdpram72.vhd