My Project
v0.0.16
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Signals | |
trig_pulse | std_logic := ' 0 ' |
control_reg | ipb_reg_v ( 1 downto 0 ) |
null_status | ipb_reg_v ( 0 downto 0 ) := ( others = > ( others = > ' 0 ' ) ) |
wbstart | std_logic_vector ( 31 downto 0 ) |
Instantiations | |
wbstart_reg | ipbus_ctrlreg_v <Entity ipbus_ctrlreg_v> |
config | reconfigure_fsm <Entity reconfigure_fsm> |
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Instantiation |
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Signal |
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Signal |
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Signal |
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Signal |
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Instantiation |