My Project  v0.0.16
Ports | Libraries | Use Clauses
ipbus_ttcinfo_sink Entity Reference
Inheritance diagram for ipbus_ttcinfo_sink:
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Collaboration diagram for ipbus_ttcinfo_sink:
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Entities

rtl  architecture
 

Libraries

IEEE 
UNISIM 

Use Clauses

STD_LOGIC_1164 
numeric_std 
vcomponents 
ipbus  Package <ipbus>
ipbus_reg_types  Package <ipbus_reg_types>
ftm  Package <ftm>

Ports

ipb_clk   in std_logic
ipb_rst   in std_logic
ipb_in   in ipb_wbus
ipb_out   out ipb_rbus
data_clk   in std_logic
data_in   in mgt_data
ttc_clk   in std_logic
crc_error   out std_logic
L1A   out std_logic
BCR   out std_logic
ECR   out std_logic
ttc_info_delay   out std_logic_vector ( 6 downto 0 )
tx_ecr   out std_logic

Member Data Documentation

◆ BCR

BCR out std_logic
Port

◆ crc_error

crc_error out std_logic
Port

◆ data_clk

data_clk in std_logic
Port

◆ data_in

data_in in mgt_data
Port

◆ ECR

ECR out std_logic
Port

◆ ftm

ftm
Package

◆ IEEE

IEEE
Library

◆ ipb_clk

ipb_clk in std_logic
Port

◆ ipb_in

ipb_in in ipb_wbus
Port

◆ ipb_out

ipb_out out ipb_rbus
Port

◆ ipb_rst

ipb_rst in std_logic
Port

◆ ipbus

ipbus
Package

◆ ipbus_reg_types

ipbus_reg_types
Package

◆ L1A

L1A out std_logic
Port

◆ numeric_std

numeric_std
Package

◆ STD_LOGIC_1164

STD_LOGIC_1164
Package

◆ ttc_clk

ttc_clk in std_logic
Port

◆ ttc_info_delay

ttc_info_delay out std_logic_vector ( 6 downto 0 )
Port

◆ tx_ecr

tx_ecr out std_logic
Port

◆ UNISIM

UNISIM
Library

◆ vcomponents

vcomponents
Package

The documentation for this class was generated from the following file: