My Project  v0.0.16
Signals | Constants | Processes
rtl Architecture Reference

Processes

transitions  ( ipbus_clk , lock , previous_lock )
key_op  ( ipbus_clk , access_key , lock , previous_lock )
writeop  ( ipbus_clk , addr , ipbus_in .ipb_wdata , ipbus_in .ipb_strobe , ipbus_in .ipb_write , ack )
timeout_flag  ( ipbus_clk , timeout , lock , ipbus_in .ipb_wdata ( 0 ) )
pulseop  ( ipbus_clk , addr , ipbus_in .ipb_wdata , ipbus_in .ipb_strobe , ipbus_in .ipb_write )
ticker  ( reset , ipbus_clk )
watchdog_timer  ( ipbus_clk , tick1ms )

Constants

timer_padding  std_logic_vector ( 31 downto TIMER_WIDTH ) := ( others = > ' 0 ' )

Signals

addr  natural range 0 to 7
ack  std_logic := ' 0 '
timeout_value  std_logic_vector ( TIMER_WIDTH - 1 downto 0 ) := std_logic_vector ( to_unsigned ( DEFAULT_TIMEOUT , TIMER_WIDTH ) )
access_key  unsigned ( 29 downto 0 ) := ( others = > ' 0 ' )
lock  std_logic := ' 0 '
previous_lock  std_logic := ' 0 '
poslock  std_logic := ' 0 '
neglock  std_logic := ' 0 '
tick1ms  std_logic
wr_timer  std_logic := ' 0 '
wr_error  std_logic := ' 0 '
timer_running  std_logic := ' 0 '
previous_timer_running  std_logic := ' 0 '
timeout  std_logic := ' 0 '
t_error  std_logic := ' 0 '

Member Function Documentation

◆ key_op()

key_op (   ipbus_clk ,
  access_key ,
  lock ,
  previous_lock  
)
Process

◆ pulseop()

pulseop (   ipbus_clk ,
  addr ,
  ipbus_in .ipb_wdata ,
  ipbus_in .ipb_strobe ,
  ipbus_in .ipb_write  
)
Process

◆ ticker()

ticker (   reset ,
  ipbus_clk  
)
Process

◆ timeout_flag()

timeout_flag (   ipbus_clk ,
  timeout ,
  lock ,
  ipbus_in .ipb_wdata ( 0 )  
)
Process

◆ transitions()

transitions (   ipbus_clk ,
  lock ,
  previous_lock  
)
Process

◆ watchdog_timer()

watchdog_timer (   ipbus_clk ,
  tick1ms  
)
Process

◆ writeop()

writeop (   ipbus_clk ,
  addr ,
  ipbus_in .ipb_wdata ,
  ipbus_in .ipb_strobe ,
  ipbus_in .ipb_write ,
  ack  
)
Process

Member Data Documentation

◆ access_key

access_key unsigned ( 29 downto 0 ) := ( others = > ' 0 ' )
Signal

◆ ack

ack std_logic := ' 0 '
Signal

◆ addr

addr natural range 0 to 7
Signal

◆ lock

lock std_logic := ' 0 '
Signal

◆ neglock

neglock std_logic := ' 0 '
Signal

◆ poslock

poslock std_logic := ' 0 '
Signal

◆ previous_lock

previous_lock std_logic := ' 0 '
Signal

◆ previous_timer_running

previous_timer_running std_logic := ' 0 '
Signal

◆ t_error

t_error std_logic := ' 0 '
Signal

◆ tick1ms

tick1ms std_logic
Signal

◆ timeout

timeout std_logic := ' 0 '
Signal

◆ timeout_value

timeout_value std_logic_vector ( TIMER_WIDTH - 1 downto 0 ) := std_logic_vector ( to_unsigned ( DEFAULT_TIMEOUT , TIMER_WIDTH ) )
Signal

◆ timer_padding

timer_padding std_logic_vector ( 31 downto TIMER_WIDTH ) := ( others = > ' 0 ' )
Constant

◆ timer_running

timer_running std_logic := ' 0 '
Signal

◆ wr_error

wr_error std_logic := ' 0 '
Signal

◆ wr_timer

wr_timer std_logic := ' 0 '
Signal

The documentation for this class was generated from the following file: