mac_arbiter Entity Reference

Inheritance diagram for mac_arbiter:

Entities
rtl	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
numeric_std
mac_arbiter_decl	Package <mac_arbiter_decl>

Generics
NSRC	positive

Ports
mac_clk	in std_logic
rst_macclk	in std_logic
src_tx_data_bus	in mac_arbiter_slv_array ( NSRC - 1 downto 0 )
src_tx_valid_bus	in mac_arbiter_sl_array ( NSRC - 1 downto 0 )
src_tx_last_bus	in mac_arbiter_sl_array ( NSRC - 1 downto 0 )
src_tx_error_bus	in mac_arbiter_sl_array ( NSRC - 1 downto 0 )
src_tx_ready_bus	out mac_arbiter_sl_array ( NSRC - 1 downto 0 )
mac_tx_data	out std_logic_vector ( 7 downto 0 )
mac_tx_valid	out std_logic
mac_tx_last	out std_logic
mac_tx_error	out std_logic
mac_tx_ready	in std_logic

Member Data Documentation

IEEE

IEEE

Library

mac_arbiter_decl

mac_arbiter_decl

Package

mac_clk

mac_clk in std_logic

Port

mac_tx_data

mac_tx_data out std_logic_vector ( 7 downto 0 )

Port

mac_tx_error

mac_tx_error out std_logic

Port

mac_tx_last

mac_tx_last out std_logic

Port

mac_tx_ready

mac_tx_ready in std_logic

Port

mac_tx_valid

mac_tx_valid out std_logic

Port

NSRC

NSRC positive

Generic

numeric_std

numeric_std

Package

rst_macclk

rst_macclk in std_logic

Port

src_tx_data_bus

src_tx_data_bus in mac_arbiter_slv_array ( NSRC - 1 downto 0 )

Port

src_tx_error_bus

src_tx_error_bus in mac_arbiter_sl_array ( NSRC - 1 downto 0 )

Port

src_tx_last_bus

src_tx_last_bus in mac_arbiter_sl_array ( NSRC - 1 downto 0 )

Port

src_tx_ready_bus

src_tx_ready_bus out mac_arbiter_sl_array ( NSRC - 1 downto 0 )

Port

src_tx_valid_bus

src_tx_valid_bus in mac_arbiter_sl_array ( NSRC - 1 downto 0 )

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/hdl/mac_arbiter.vhd