My Project  v0.0.16
Ports | Libraries | Use Clauses
mac_bridge_slave Entity Reference

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 

Ports

gt_clk_p   in std_logic
gt_clk_n   in std_logic
gt_tx_p   out std_logic
gt_tx_n   out std_logic
gt_rx_p   in std_logic
gt_rx_n   in std_logic
clk125_out   out std_logic
clk125_fr   out std_logic
rsti   in std_logic
locked   out std_logic
tx_data   in std_logic_vector ( 7 downto 0 )
tx_valid   in std_logic
tx_last   in std_logic
tx_error   in std_logic
tx_ready   out std_logic
rx_data   out std_logic_vector ( 7 downto 0 )
rx_valid   out std_logic
rx_last   out std_logic
rx_error   out std_logic

Member Data Documentation

◆ clk125_fr

clk125_fr out std_logic
Port

◆ clk125_out

clk125_out out std_logic
Port

◆ gt_clk_n

gt_clk_n in std_logic
Port

◆ gt_clk_p

gt_clk_p in std_logic
Port

◆ gt_rx_n

gt_rx_n in std_logic
Port

◆ gt_rx_p

gt_rx_p in std_logic
Port

◆ gt_tx_n

gt_tx_n out std_logic
Port

◆ gt_tx_p

gt_tx_p out std_logic
Port

◆ ieee

ieee
Library

◆ locked

locked out std_logic
Port

◆ rsti

rsti in std_logic
Port

◆ rx_data

rx_data out std_logic_vector ( 7 downto 0 )
Port

◆ rx_error

rx_error out std_logic
Port

◆ rx_last

rx_last out std_logic
Port

◆ rx_valid

rx_valid out std_logic
Port

◆ std_logic_1164

std_logic_1164
Package

◆ tx_data

tx_data in std_logic_vector ( 7 downto 0 )
Port

◆ tx_error

tx_error in std_logic
Port

◆ tx_last

tx_last in std_logic
Port

◆ tx_ready

tx_ready out std_logic
Port

◆ tx_valid

tx_valid in std_logic
Port

The documentation for this class was generated from the following file: