| CORE_GENERATION_INFO mac_fifo_axi4_arch : architecture is " mac_fifo_axi4 , fifo_generator_v13_2_5 , {x_ipProduct = Vivado 2019.2 , x_ipVendor = xilinx.com , x_ipLibrary = ip , x_ipName = fifo_generator , x_ipVersion = 13.2 , x_ipCoreRevision = 5 , x_ipLanguage = VHDL , x_ipSimLanguage = MIXED , C_COMMON_CLOCK = 0 , C_SELECT_XPM = 0 , C_COUNT_TYPE = 0 , C_DATA_COUNT_WIDTH = 10 , C_DEFAULT_VALUE = BlankString , C_DIN_WIDTH = 18 , C_DOUT_RST_VAL = 0 , C_DOUT_WIDTH = 18 , C_ENABLE_RLOCS = 0 , C_FAMILY = kintex7 , C_FULL_FLAGS_RST_VAL = 1 , C_HAS_ALMOST_EMPTY = 0 , C_HAS_ALMOST_FULL = 0 , C_HAS_BACKUP = 0 , C_HAS_DATA_COUNT = 0 , C_HAS_INT_CLK = 0 , C_HAS_ " & " MEMINIT_FILE = 0 , C_HAS_OVERFLOW = 0 , C_HAS_RD_DATA_COUNT = 0 , C_HAS_RD_RST = 0 , C_HAS_RST = 1 , C_HAS_SRST = 0 , C_HAS_UNDERFLOW = 0 , C_HAS_VALID = 0 , C_HAS_WR_ACK = 0 , C_HAS_WR_DATA_COUNT = 0 , C_HAS_WR_RST = 0 , C_IMPLEMENTATION_TYPE = 0 , C_INIT_WR_PNTR_VAL = 0 , C_MEMORY_TYPE = 1 , C_MIF_FILE_NAME = BlankString , C_OPTIMIZATION_MODE = 0 , C_OVERFLOW_LOW = 0 , C_PRELOAD_LATENCY = 1 , C_PRELOAD_REGS = 0 , C_PRIM_FIFO_TYPE = 4kx4 , C_PROG_EMPTY_THRESH_ASSERT_VAL = 2 , C_PROG_EMPTY_THRESH_NEGATE_VAL = 3 , C_PROG_EMPTY_TYPE = 0 , C_PROG_FULL_THRESH_ASSERT_VAL = 1022 , C_PROG_FULL_TH " & " RESH_NEGATE_VAL = 1021 , C_PROG_FULL_TYPE = 0 , C_RD_DATA_COUNT_WIDTH = 10 , C_RD_DEPTH = 1024 , C_RD_FREQ = 1 , C_RD_PNTR_WIDTH = 10 , C_UNDERFLOW_LOW = 0 , C_USE_DOUT_RST = 1 , C_USE_ECC = 0 , C_USE_EMBEDDED_REG = 0 , C_USE_PIPELINE_REG = 0 , C_POWER_SAVING_MODE = 0 , C_USE_FIFO16_FLAGS = 0 , C_USE_FWFT_DATA_COUNT = 0 , C_VALID_LOW = 0 , C_WR_ACK_LOW = 0 , C_WR_DATA_COUNT_WIDTH = 10 , C_WR_DEPTH = 1024 , C_WR_FREQ = 1 , C_WR_PNTR_WIDTH = 10 , C_WR_RESPONSE_LATENCY = 1 , C_MSGON_VAL = 0 , C_ENABLE_RST_SYNC = 1 , C_EN_SAFETY_CKT = 0 , C_ERROR_INJECTION_TYPE = 0 , C_SYNCHRONIZER_STAGE = 2 , C_INTER " & " FACE_TYPE = 1 , C_AXI_TYPE = 1 , C_HAS_AXI_WR_CHANNEL = 1 , C_HAS_AXI_RD_CHANNEL = 1 , C_HAS_SLAVE_CE = 0 , C_HAS_MASTER_CE = 0 , C_ADD_NGC_CONSTRAINT = 0 , C_USE_COMMON_OVERFLOW = 0 , C_USE_COMMON_UNDERFLOW = 0 , C_USE_DEFAULT_SETTINGS = 0 , C_AXI_ID_WIDTH = 1 , C_AXI_ADDR_WIDTH = 32 , C_AXI_DATA_WIDTH = 64 , C_AXI_LEN_WIDTH = 8 , C_AXI_LOCK_WIDTH = 1 , C_HAS_AXI_ID = 0 , C_HAS_AXI_AWUSER = 0 , C_HAS_AXI_WUSER = 0 , C_HAS_AXI_BUSER = 0 , C_HAS_AXI_ARUSER = 0 , C_HAS_AXI_RUSER = 0 , C_AXI_ARUSER_WIDTH = 1 , C_AXI_AWUSER_WIDTH = 1 , C_AXI_WUSER_WIDTH = 1 , C_AXI_BUSER_WIDTH = 1 , C_AXI_RUSER_WI " & " DTH = 1 , C_HAS_AXIS_TDATA = 1 , C_HAS_AXIS_TID = 0 , C_HAS_AXIS_TDEST = 0 , C_HAS_AXIS_TUSER = 1 , C_HAS_AXIS_TREADY = 1 , C_HAS_AXIS_TLAST = 1 , C_HAS_AXIS_TSTRB = 0 , C_HAS_AXIS_TKEEP = 0 , C_AXIS_TDATA_WIDTH = 8 , C_AXIS_TID_WIDTH = 1 , C_AXIS_TDEST_WIDTH = 1 , C_AXIS_TUSER_WIDTH = 1 , C_AXIS_TSTRB_WIDTH = 1 , C_AXIS_TKEEP_WIDTH = 1 , C_WACH_TYPE = 0 , C_WDCH_TYPE = 0 , C_WRCH_TYPE = 0 , C_RACH_TYPE = 0 , C_RDCH_TYPE = 0 , C_AXIS_TYPE = 0 , C_IMPLEMENTATION_TYPE_WACH = 12 , C_IMPLEMENTATION_TYPE_WDCH = 11 , C_IMPLEMENTATION_TYPE_WRCH = 12 , C_IMPLEMENTATION_TYPE_RACH = 12 , C_IMPLEMENTATIO " & " N_TYPE_RDCH = 11 , C_IMPLEMENTATION_TYPE_AXIS = 12 , C_APPLICATION_TYPE_WACH = 0 , C_APPLICATION_TYPE_WDCH = 0 , C_APPLICATION_TYPE_WRCH = 0 , C_APPLICATION_TYPE_RACH = 0 , C_APPLICATION_TYPE_RDCH = 0 , C_APPLICATION_TYPE_AXIS = 0 , C_PRIM_FIFO_TYPE_WACH = 512x36 , C_PRIM_FIFO_TYPE_WDCH = 1kx36 , C_PRIM_FIFO_TYPE_WRCH = 512x36 , C_PRIM_FIFO_TYPE_RACH = 512x36 , C_PRIM_FIFO_TYPE_RDCH = 1kx36 , C_PRIM_FIFO_TYPE_AXIS = 512x36 , C_USE_ECC_WACH = 0 , C_USE_ECC_WDCH = 0 , C_USE_ECC_WRCH = 0 , C_USE_ECC_RACH = 0 , C_USE_ECC_RDCH = 0 , C_USE_ECC_AXIS = 0 , C_ERROR_INJECTION_TYPE_WA " & " CH = 0 , C_ERROR_INJECTION_TYPE_WDCH = 0 , C_ERROR_INJECTION_TYPE_WRCH = 0 , C_ERROR_INJECTION_TYPE_RACH = 0 , C_ERROR_INJECTION_TYPE_RDCH = 0 , C_ERROR_INJECTION_TYPE_AXIS = 0 , C_DIN_WIDTH_WACH = 32 , C_DIN_WIDTH_WDCH = 64 , C_DIN_WIDTH_WRCH = 2 , C_DIN_WIDTH_RACH = 32 , C_DIN_WIDTH_RDCH = 64 , C_DIN_WIDTH_AXIS = 10 , C_WR_DEPTH_WACH = 16 , C_WR_DEPTH_WDCH = 1024 , C_WR_DEPTH_WRCH = 16 , C_WR_DEPTH_RACH = 16 , C_WR_DEPTH_RDCH = 1024 , C_WR_DEPTH_AXIS = 16 , C_WR_PNTR_WIDTH_WACH = 4 , C_WR_PNTR_WIDTH_WDCH = 10 , C_WR_PNTR_WIDTH_WRCH = 4 , C_WR_PNTR_WIDTH_RACH = 4 , C_WR_PNTR_WIDTH " & " _RDCH = 10 , C_WR_PNTR_WIDTH_AXIS = 4 , C_HAS_DATA_COUNTS_WACH = 0 , C_HAS_DATA_COUNTS_WDCH = 0 , C_HAS_DATA_COUNTS_WRCH = 0 , C_HAS_DATA_COUNTS_RACH = 0 , C_HAS_DATA_COUNTS_RDCH = 0 , C_HAS_DATA_COUNTS_AXIS = 0 , C_HAS_PROG_FLAGS_WACH = 0 , C_HAS_PROG_FLAGS_WDCH = 0 , C_HAS_PROG_FLAGS_WRCH = 0 , C_HAS_PROG_FLAGS_RACH = 0 , C_HAS_PROG_FLAGS_RDCH = 0 , C_HAS_PROG_FLAGS_AXIS = 0 , C_PROG_FULL_TYPE_WACH = 0 , C_PROG_FULL_TYPE_WDCH = 0 , C_PROG_FULL_TYPE_WRCH = 0 , C_PROG_FULL_TYPE_RACH = 0 , C_PROG_FULL_TYPE_RDCH = 0 , C_PROG_FULL_TYPE_AXIS = 0 , C_PROG_FULL_THRESH_ASSERT_VAL_ " & " WACH = 15 , C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 1023 , C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 15 , C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 15 , C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 1023 , C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 15 , C_PROG_EMPTY_TYPE_WACH = 0 , C_PROG_EMPTY_TYPE_WDCH = 0 , C_PROG_EMPTY_TYPE_WRCH = 0 , C_PROG_EMPTY_TYPE_RACH = 0 , C_PROG_EMPTY_TYPE_RDCH = 0 , C_PROG_EMPTY_TYPE_AXIS = 0 , C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 13 , C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 1021 , C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 13 , C_PROG_EMPTY_THRESH_ASSERT_VA " & " L_RACH = 13 , C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 1021 , C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 13 , C_REG_SLICE_MODE_WACH = 0 , C_REG_SLICE_MODE_WDCH = 0 , C_REG_SLICE_MODE_WRCH = 0 , C_REG_SLICE_MODE_RACH = 0 , C_REG_SLICE_MODE_RDCH = 0 , C_REG_SLICE_MODE_AXIS = 0} " |
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