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My Project
v0.0.16
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Entities | |
| rtl | architecture |
Libraries | |
| IEEE | |
Use Clauses | |
| STD_LOGIC_1164 | |
| ipbus | Package <ipbus> |
| ipbus_trans_decl | Package <ipbus_trans_decl> |
| ipbus_reg_types | Package <ipbus_reg_types> |
| ipbus_decode_mp7_ctrl | |
| top_decl | Package <top_decl> |
Generics | |
| FW_REV | std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) |
Ports | |
| clk | in std_logic |
| rst | in std_logic |
| ipb_in | in ipb_wbus |
| ipb_out | out ipb_rbus |
| nuke | out std_logic |
| soft_rst | out std_logic |
| qsel | out std_logic_vector ( 7 downto 0 ) |
| ppsel | out std_logic_vector ( 5 downto 0 ) |
| pp_data_sel | out std_logic |
| board_loc | out std_logic_vector ( 31 downto 0 ) |
| debug | in std_logic_vector ( 7 downto 0 ) := X " 00 " |
| clk40_rst | out std_logic |
| clk40_sel | out std_logic |
| clk40_lock | in std_logic |
| clk40_stop | in std_logic |
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1.8.13