My Project  v0.0.16
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osum_crc9d32 Entity Reference
Inheritance diagram for osum_crc9d32:
Inheritance graph
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Entities

behavioral  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 

Generics

REVERSE_BIT_ORDER  boolean := false

Ports

clock   in std_logic
crc_start   in std_logic
d_in   in std_logic_vector ( 31 downto 0 )
crc_out   out std_logic_vector ( 8 downto 0 )

Member Data Documentation

◆ clock

clock in std_logic
Port

◆ crc_out

crc_out out std_logic_vector ( 8 downto 0 )
Port

◆ crc_start

crc_start in std_logic
Port

◆ d_in

d_in in std_logic_vector ( 31 downto 0 )
Port

◆ ieee

ieee
Library

◆ numeric_std

numeric_std
Package

◆ REVERSE_BIT_ORDER

REVERSE_BIT_ORDER boolean := false
Generic

◆ std_logic_1164

std_logic_1164
Package

The documentation for this class was generated from the following file: