patterngen Entity Reference

Entities
rtl	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_unsigned
dss

Generics
COUNT_WIDTH	natural := 8

Ports
clk	in std_logic
rst_b	in std_logic
q	out std_logic_vector ( COUNT_WIDTH - 1 downto 0 )
p	out std_logic

Member Data Documentation

clk

clk in std_logic

Port

COUNT_WIDTH

COUNT_WIDTH natural := 8

Generic

dss

dss

Package

ieee

ieee

Library

p

p out std_logic

Port

q

q out std_logic_vector ( COUNT_WIDTH - 1 downto 0 )

Port

rst_b

rst_b in std_logic

Port

std_logic_1164

std_logic_1164

Package

std_logic_unsigned

std_logic_unsigned

Package

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The documentation for this class was generated from the following file:

• common/Misc/hdl/patterngen.vhd