rtl Architecture Reference

Processes
writeop	( ipbus_clk , addr , ipbus_in .ipb_wdata , ipbus_in .ipb_strobe , ipbus_in .ipb_write , ack )

Constants
COMPLETE_FRAMES	natural := ( 2 ** ADDR_WIDTH ) / FRAME_SIZE
DEFAULT_SINK_DELAY	std_logic_vector ( 4 downto 0 ) := std_logic_vector ( to_unsigned ( 2 , 5 ) )

Signals
ack	std_logic
addr	natural range 0 to 7
controlreg	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
pulsereg	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
run_playback_int	std_logic := ' 0 '
run	std_logic := ' 0 '
link_latency	std_logic_vector ( 4 downto 0 ) := DEFAULT_SINK_DELAY

Member Function Documentation

writeop()

writeop (   ipbus_clk ,   addr ,   ipbus_in .ipb_wdata ,   ipbus_in .ipb_strobe ,   ipbus_in .ipb_write ,   ack   )

Process

Member Data Documentation

ack

ack std_logic

Signal

addr

addr natural range 0 to 7

Signal

COMPLETE_FRAMES

COMPLETE_FRAMES natural := ( 2 ** ADDR_WIDTH ) / FRAME_SIZE

Constant

controlreg

controlreg std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Signal

DEFAULT_SINK_DELAY

DEFAULT_SINK_DELAY std_logic_vector ( 4 downto 0 ) := std_logic_vector ( to_unsigned ( 2 , 5 ) )

Constant

link_latency

link_latency std_logic_vector ( 4 downto 0 ) := DEFAULT_SINK_DELAY

Signal

pulsereg

pulsereg std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Signal

run

run std_logic := ' 0 '

Signal

run_playback_int

run_playback_int std_logic := ' 0 '

Signal

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The documentation for this class was generated from the following file:

• common/DSS_buffer/hdl/playback_control.vhd