behavioral Architecture Reference

Processes
PROCESS_0	( SYSCLK )
PROCESS_1	( SYSCLK )

Constants
MAX_COUNT	integer := 320

Types
FSM_STATE	( IDLE , DATA_00 , DATA_01 , DATA_02 , DATA_03 , DATA_04 , DATA_05 , DATA_06 , DATA_07 )

Signals
NEXT_STATE	FSM_STATE := IDLE
CE_n	std_logic := ' 1 '
ICAP_DATA	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ICAP_WRITE_n	std_logic := ' 1 '
ICAP_DATA_BITSWAP	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
reconfig_delay	integer range 0 to MAX_COUNT := 0
trigger_reconfig	std_logic := ' 0 '

Attributes
dont_touch	string
dont_touch	ICAP_DATA : signal is " true "
dont_touch	ICAP_WRITE_n : signal is " true "
dont_touch	CE_n : signal is " true "

Instantiations
icape2_inst	icape2

Member Function Documentation

PROCESS_0()

PROCESS_0 (   SYSCLK   )

Process

PROCESS_1()

PROCESS_1

(

SYSCLK

)

Member Data Documentation

CE_n

CE_n std_logic := ' 1 '

Signal

dont_touch [1/4]

dont_touch string

Attribute

dont_touch [2/4]

dont_touch ICAP_DATA : signal is " true "

Attribute

dont_touch [3/4]

dont_touch ICAP_WRITE_n : signal is " true "

Attribute

dont_touch [4/4]

dont_touch CE_n : signal is " true "

Attribute

FSM_STATE

FSM_STATE ( IDLE , DATA_00 , DATA_01 , DATA_02 , DATA_03 , DATA_04 , DATA_05 , DATA_06 , DATA_07 )

Type

ICAP_DATA

ICAP_DATA std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

ICAP_DATA_BITSWAP

ICAP_DATA_BITSWAP std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

ICAP_WRITE_n

ICAP_WRITE_n std_logic := ' 1 '

Signal

icape2_inst

icape2_inst icape2

Instantiation

MAX_COUNT

MAX_COUNT integer := 320

Constant

NEXT_STATE

NEXT_STATE FSM_STATE := IDLE

Signal

reconfig_delay

reconfig_delay integer range 0 to MAX_COUNT := 0

Signal

trigger_reconfig

trigger_reconfig std_logic := ' 0 '

Signal

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The documentation for this class was generated from the following file:

• common/Configure/hdl/reconfigure_fsm.vhd