My Project
v0.0.16
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Entities | |
rtl | architecture |
Libraries | |
IEEE |
Use Clauses | |
STD_LOGIC_1164 | |
numeric_std | |
sync_config | Package <sync_config> |
Generics | |
FRAME_SIZE | natural |
Ports | |
data_clk | in STD_LOGIC |
data | in std_logic_vector ( 31 downto 0 ) |
ctrl | in std_logic_vector ( 3 downto 0 ) |
eof | out std_logic |
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Port |
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Port |
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Port |
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Port |
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Generic |
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Library |
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Package |
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Package |
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Package |