sdpram_16x10_32x9 Entity Reference

Inheritance diagram for sdpram_16x10_32x9:

Entities
sdpram_16x10_32x9_a	architecture
sdpram_16x10_32x9_arch	architecture

Libraries
ieee
XilinxCoreLib
blk_mem_gen_v8_2

Use Clauses
std_logic_1164
numeric_std
blk_mem_gen_v8_2

Ports
clka	in STD_LOGIC
wea	in STD_LOGIC_VECTOR ( 0 DOWNTO 0 )
addra	in STD_LOGIC_VECTOR ( 9 DOWNTO 0 )
dina	in STD_LOGIC_VECTOR ( 15 DOWNTO 0 )
clkb	in STD_LOGIC
addrb	in STD_LOGIC_VECTOR ( 8 DOWNTO 0 )
doutb	out STD_LOGIC_VECTOR ( 31 DOWNTO 0 )

Member Data Documentation

addra

addra in STD_LOGIC_VECTOR ( 9 DOWNTO 0 )

Port

addrb

addrb in STD_LOGIC_VECTOR ( 8 DOWNTO 0 )

Port

blk_mem_gen_v8_2 [1/2]

blk_mem_gen_v8_2

Library

blk_mem_gen_v8_2 [2/2]

blk_mem_gen_v8_2

Package

clka

clka in STD_LOGIC

Port

clkb

clkb in STD_LOGIC

Port

dina

dina in STD_LOGIC_VECTOR ( 15 DOWNTO 0 )

Port

doutb

doutb out STD_LOGIC_VECTOR ( 31 DOWNTO 0 )

Port

ieee

ieee

Library

numeric_std

numeric_std

Package

std_logic_1164

std_logic_1164

Package

wea

wea in STD_LOGIC_VECTOR ( 0 DOWNTO 0 )

Port

XilinxCoreLib

XilinxCoreLib

Library

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The documentation for this class was generated from the following file:

• components/ipbus_slaves/firmware/cgn/sdpram_16x10_32x9.vhd