sdpram_32x9_16x10_arch Architecture Reference

Collaboration diagram for sdpram_32x9_16x10_arch:

Components
blk_mem_gen_v8_2

Attributes
DowngradeIPIdentifiedWarnings	string
DowngradeIPIdentifiedWarnings	sdpram_32x9_16x10_arch : architecture is " yes "
X_CORE_INFO	STRING
X_CORE_INFO	sdpram_32x9_16x10_arch : architecture is " blk_mem_gen_v8_2 , Vivado 2015.2 "
CHECK_LICENSE_TYPE	STRING
CHECK_LICENSE_TYPE	sdpram_32x9_16x10_arch : architecture is " sdpram_32x9_16x10 , blk_mem_gen_v8_2 , {} "
CORE_GENERATION_INFO	STRING
CORE_GENERATION_INFO	sdpram_32x9_16x10_arch : architecture is " sdpram_32x9_16x10 , blk_mem_gen_v8_2 , {x_ipProduct = Vivado 2015.2 , x_ipVendor = xilinx.com , x_ipLibrary = ip , x_ipName = blk_mem_gen , x_ipVersion = 8.2 , x_ipCoreRevision = 6 , x_ipLanguage = VHDL , x_ipSimLanguage = MIXED , C_FAMILY = virtex7 , C_XDEVICEFAMILY = virtex7 , C_ELABORATION_DIR = ./ , C_INTERFACE_TYPE = 0 , C_AXI_TYPE = 1 , C_AXI_SLAVE_TYPE = 0 , C_USE_BRAM_BLOCK = 0 , C_ENABLE_32BIT_ADDRESS = 0 , C_CTRL_ECC_ALGO = NONE , C_HAS_AXI_ID = 0 , C_AXI_ID_WIDTH = 4 , C_MEM_TYPE = 1 , C_BYTE_SIZE = 9 , C_ALGORITHM = 1 , C_PRIM_TYPE = 1 , C_LOAD_INIT_FILE = 0 , C_INIT_FILE_NAME = no_coe_file_loaded , C_INIT_FILE = sdpram_32x9_16x10.mem , C_USE_DEFAULT_DATA = 0 , C_DEFAULT_DATA = 0 , C_HAS_RSTA = 0 , C_RST_PRIORITY_A = CE , C_RSTRAM_A = 0 , C_INITA_VAL = 0 , C_HAS_ENA = 0 , C_HAS_REGCEA = 0 , C_USE_BYTE_WEA = 0 , C_WEA_WIDTH = 1 , C_WRITE_MODE_A = WRITE_FIRST , C_WRITE_WIDTH_A = 32 , C_READ_WIDTH_A = 32 , C_WRITE_DEPTH_A = 512 , C_READ_DEPTH_A = 512 , C_ADDRA_WIDTH = 9 , C_HAS_RSTB = 0 , C_RST_PRIORITY_B = CE , C_RSTRAM_B = 0 , C_INITB_VAL = 0 , C_HAS_ENB = 0 , C_HAS_REGCEB = 0 , C_USE_BYTE_WEB = 0 , C_WEB_WIDTH = 1 , C_WRITE_MODE_B = WRITE_FIRST , C_WRITE_WIDTH_B = 16 , C_READ_WIDTH_B = 16 , C_WRITE_DEPTH_B = 1024 , C_READ_DEPTH_B = 1024 , C_ADDRB_WIDTH = 10 , C_HAS_MEM_OUTPUT_REGS_A = 0 , C_HAS_MEM_OUTPUT_REGS_B = 0 , C_HAS_MUX_OUTPUT_REGS_A = 0 , C_HAS_MUX_OUTPUT_REGS_B = 0 , C_MUX_PIPELINE_STAGES = 0 , C_HAS_SOFTECC_INPUT_REGS_A = 0 , C_HAS_SOFTECC_OUTPUT_REGS_B = 0 , C_USE_SOFTECC = 0 , C_USE_ECC = 0 , C_EN_ECC_PIPE = 0 , C_HAS_INJECTERR = 0 , C_SIM_COLLISION_CHECK = NONE , C_COMMON_CLK = 0 , C_DISABLE_WARN_BHV_COLL = 1 , C_EN_SLEEP_PIN = 0 , C_USE_URAM = 0 , C_EN_RDADDRA_CHG = 0 , C_EN_RDADDRB_CHG = 0 , C_EN_DEEPSLEEP_PIN = 0 , C_EN_SHUTDOWN_PIN = 0 , C_DISABLE_WARN_BHV_RANGE = 1 , C_COUNT_36K_BRAM = 0 , C_COUNT_18K_BRAM = 1 , C_EST_POWER_SUMMARY = Estimated Power for IP _ 2.73765 mW} "
X_INTERFACE_INFO	STRING
X_INTERFACE_INFO	clka : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTA CLK "
X_INTERFACE_INFO	wea : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTA WE "
X_INTERFACE_INFO	addra : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTA ADDR "
X_INTERFACE_INFO	dina : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTA DIN "
X_INTERFACE_INFO	clkb : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTB CLK "
X_INTERFACE_INFO	addrb : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTB ADDR "
X_INTERFACE_INFO	doutb : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTB DOUT "

Instantiations
u0	blk_mem_gen_v8_2

Member Data Documentation

blk_mem_gen_v8_2

blk_mem_gen_v8_2

Component

CHECK_LICENSE_TYPE [1/2]

CHECK_LICENSE_TYPE STRING

Attribute

CHECK_LICENSE_TYPE [2/2]

CHECK_LICENSE_TYPE sdpram_32x9_16x10_arch : architecture is " sdpram_32x9_16x10 , blk_mem_gen_v8_2 , {} "

Attribute

CORE_GENERATION_INFO [1/2]

CORE_GENERATION_INFO STRING

Attribute

CORE_GENERATION_INFO [2/2]

CORE_GENERATION_INFO sdpram_32x9_16x10_arch : architecture is " sdpram_32x9_16x10 , blk_mem_gen_v8_2 , {x_ipProduct = Vivado 2015.2 , x_ipVendor = xilinx.com , x_ipLibrary = ip , x_ipName = blk_mem_gen , x_ipVersion = 8.2 , x_ipCoreRevision = 6 , x_ipLanguage = VHDL , x_ipSimLanguage = MIXED , C_FAMILY = virtex7 , C_XDEVICEFAMILY = virtex7 , C_ELABORATION_DIR = ./ , C_INTERFACE_TYPE = 0 , C_AXI_TYPE = 1 , C_AXI_SLAVE_TYPE = 0 , C_USE_BRAM_BLOCK = 0 , C_ENABLE_32BIT_ADDRESS = 0 , C_CTRL_ECC_ALGO = NONE , C_HAS_AXI_ID = 0 , C_AXI_ID_WIDTH = 4 , C_MEM_TYPE = 1 , C_BYTE_SIZE = 9 , C_ALGORITHM = 1 , C_PRIM_TYPE = 1 , C_LOAD_INIT_FILE = 0 , C_INIT_FILE_NAME = no_coe_file_loaded , C_INIT_FILE = sdpram_32x9_16x10.mem , C_USE_DEFAULT_DATA = 0 , C_DEFAULT_DATA = 0 , C_HAS_RSTA = 0 , C_RST_PRIORITY_A = CE , C_RSTRAM_A = 0 , C_INITA_VAL = 0 , C_HAS_ENA = 0 , C_HAS_REGCEA = 0 , C_USE_BYTE_WEA = 0 , C_WEA_WIDTH = 1 , C_WRITE_MODE_A = WRITE_FIRST , C_WRITE_WIDTH_A = 32 , C_READ_WIDTH_A = 32 , C_WRITE_DEPTH_A = 512 , C_READ_DEPTH_A = 512 , C_ADDRA_WIDTH = 9 , C_HAS_RSTB = 0 , C_RST_PRIORITY_B = CE , C_RSTRAM_B = 0 , C_INITB_VAL = 0 , C_HAS_ENB = 0 , C_HAS_REGCEB = 0 , C_USE_BYTE_WEB = 0 , C_WEB_WIDTH = 1 , C_WRITE_MODE_B = WRITE_FIRST , C_WRITE_WIDTH_B = 16 , C_READ_WIDTH_B = 16 , C_WRITE_DEPTH_B = 1024 , C_READ_DEPTH_B = 1024 , C_ADDRB_WIDTH = 10 , C_HAS_MEM_OUTPUT_REGS_A = 0 , C_HAS_MEM_OUTPUT_REGS_B = 0 , C_HAS_MUX_OUTPUT_REGS_A = 0 , C_HAS_MUX_OUTPUT_REGS_B = 0 , C_MUX_PIPELINE_STAGES = 0 , C_HAS_SOFTECC_INPUT_REGS_A = 0 , C_HAS_SOFTECC_OUTPUT_REGS_B = 0 , C_USE_SOFTECC = 0 , C_USE_ECC = 0 , C_EN_ECC_PIPE = 0 , C_HAS_INJECTERR = 0 , C_SIM_COLLISION_CHECK = NONE , C_COMMON_CLK = 0 , C_DISABLE_WARN_BHV_COLL = 1 , C_EN_SLEEP_PIN = 0 , C_USE_URAM = 0 , C_EN_RDADDRA_CHG = 0 , C_EN_RDADDRB_CHG = 0 , C_EN_DEEPSLEEP_PIN = 0 , C_EN_SHUTDOWN_PIN = 0 , C_DISABLE_WARN_BHV_RANGE = 1 , C_COUNT_36K_BRAM = 0 , C_COUNT_18K_BRAM = 1 , C_EST_POWER_SUMMARY = Estimated Power for IP _ 2.73765 mW} "

Attribute

DowngradeIPIdentifiedWarnings [1/2]

DowngradeIPIdentifiedWarnings string

Attribute

DowngradeIPIdentifiedWarnings [2/2]

DowngradeIPIdentifiedWarnings sdpram_32x9_16x10_arch : architecture is " yes "

Attribute

u0

u0 blk_mem_gen_v8_2

Instantiation

X_CORE_INFO [1/2]

X_CORE_INFO STRING

Attribute

X_CORE_INFO [2/2]

X_CORE_INFO sdpram_32x9_16x10_arch : architecture is " blk_mem_gen_v8_2 , Vivado 2015.2 "

Attribute

X_INTERFACE_INFO [1/8]

X_INTERFACE_INFO STRING

Attribute

X_INTERFACE_INFO [2/8]

X_INTERFACE_INFO clka : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTA CLK "

Attribute

X_INTERFACE_INFO [3/8]

X_INTERFACE_INFO wea : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTA WE "

Attribute

X_INTERFACE_INFO [4/8]

X_INTERFACE_INFO addra : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTA ADDR "

Attribute

X_INTERFACE_INFO [5/8]

X_INTERFACE_INFO dina : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTA DIN "

Attribute

X_INTERFACE_INFO [6/8]

X_INTERFACE_INFO clkb : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTB CLK "

Attribute

X_INTERFACE_INFO [7/8]

X_INTERFACE_INFO addrb : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTB ADDR "

Attribute

X_INTERFACE_INFO [8/8]

X_INTERFACE_INFO doutb : signal is " xilinx.com : interface : bram : 1.0 BRAM_PORTB DOUT "

Attribute

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The documentation for this class was generated from the following file:

• ipbus_lib/components/ipbus_slaves/firmware/cgn/sdpram_32x9_16x10.vhd