My Project  v0.0.16
Types | Signals | Processes
arc Architecture Reference

Processes

p_hammingbits8  ( d_br , hmg_br )
p_hammingbits32  ( d_adr , hmg_adr )
p_driver  ( clk )
p_synch  ( clk )
p_driver  ( clk )
p_synch  ( clk )

Types

state ( s_idle , s_fmt , s_get_data , s_get_broadcast , s_stop , s_error )

Signals

received_word  std_logic_vector ( 38 downto 0 )
brc_rdy  std_logic
dta_rdy  std_logic
serBchanR  std_logic
serBchanRR  std_logic
test_init  std_logic
test_data  std_logic_vector ( 41 downto 0 )
d_adr  std_logic_vector ( 31 downto 0 )
d_br  std_logic_vector ( 7 downto 0 )
hmg_br  std_logic_vector ( 4 downto 0 )
hmg_adr  std_logic_vector ( 6 downto 0 )
s_br  std_logic_vector ( 4 downto 0 )
s_adr  std_logic_vector ( 6 downto 0 )
next_state  state
single_bit_error_i  std_logic
double_bit_error_i  std_logic

Member Function Documentation

◆ p_driver() [1/2]

p_driver (   clk  
)
Process

◆ p_driver() [2/2]

p_driver (   clk  
)
Process

◆ p_hammingbits32()

p_hammingbits32 (   d_adr ,
  hmg_adr  
)
Process

◆ p_hammingbits8()

p_hammingbits8 (   d_br ,
  hmg_br  
)
Process

◆ p_synch() [1/2]

p_synch (   clk  
)
Process

◆ p_synch() [2/2]

p_synch (   clk  
)
Process

Member Data Documentation

◆ brc_rdy

brc_rdy std_logic
Signal

◆ d_adr

d_adr std_logic_vector ( 31 downto 0 )
Signal

◆ d_br

d_br std_logic_vector ( 7 downto 0 )
Signal

◆ double_bit_error_i

double_bit_error_i std_logic
Signal

◆ dta_rdy

dta_rdy std_logic
Signal

◆ hmg_adr

hmg_adr std_logic_vector ( 6 downto 0 )
Signal

◆ hmg_br

hmg_br std_logic_vector ( 4 downto 0 )
Signal

◆ next_state

next_state state
Signal

◆ received_word

received_word std_logic_vector ( 38 downto 0 )
Signal

◆ s_adr

s_adr std_logic_vector ( 6 downto 0 )
Signal

◆ s_br

s_br std_logic_vector ( 4 downto 0 )
Signal

◆ serBchanR

serBchanR std_logic
Signal

◆ serBchanRR

serBchanRR std_logic
Signal

◆ single_bit_error_i

single_bit_error_i std_logic
Signal

◆ state

state ( s_idle , s_fmt , s_get_data , s_get_broadcast , s_stop , s_error )
Type

◆ test_data

test_data std_logic_vector ( 41 downto 0 )
Signal

◆ test_init

test_init std_logic
Signal

The documentation for this class was generated from the following file: